/* 
00h ~ 03Fh Interrupt      64
040 ~ 8000h flash         32k
*/
/*
0000 ~ 005Fh Memory-mapped
0060 ~ 007Fh DARAM B2   32
0200 ~ 02FFh DARAM B0  256
0300 ~ 03FFh DARAM B1  256
0800 ~ 0FFFh SARAM(2K)
7000 ~ 73FFh PF1      1024
7400 ~ 743Fh PF2        64
7500 ~ 753Fh PF3        64
77F0 ~ 77F3h Code security passwords

8000 ~ FFFFh External
 */  

 /* -stack 40      */
/*            
MEMORY
{
  PAGE 0: VECS   : origin = 0h,    length = 40h    
          PVECS  : origin = 044h,  length = 3Bh    
          PROG   : origin = 080h,  length = 7F00h 
  
  PAGE 1: MMRS   : origin = 0h,    length = 60h   
          B2     : origin = 060h,  length = 020h  
          B0     : origin = 0200h, length = 100h  
          B1     : origin = 0300h, length = 100h  
          SARAM  : origin = 0800h, length = 800h  
         EXT    : origin = 8000h, length = 8000h 
}

SECTIONS
{
   .reset    : {}> VECS  PAGE 0
   .vectors  : {}> VECS  PAGE 0
   .pvecs    : {}> PVECS PAGE
   .vectors  : {}> PVECS  PAGE 0
   .text     : {}> PROG  PAGE 0                               
   .cinit    : {}> PROG  PAGE 0
   .switch   : {}> PROG  PAGE 0
   .bss      : {}> SARAM PAGE 1
   .const    : {}> SARAM PAGE 1
   .data     : {}> SARAM PAGE 1
   .sysmem   : {}> SARAM PAGE 1
   .stack    : {}> SARAM PAGE 1

}    
*/

-stack 0x100

MEMORY
{
PAGE 0:
     VECT    : o=0, length=40h
     FLASH   : o=80h, length=4000h
PAGE 1:
      
     B0B1:  origin = 0200h, length = 200h
     SARAM: origin = 0800h, length = 800h
         
}

SECTIONS
{
   .vectors  : {}> VECT  PAGE 0
   .text:  {} > FLASH PAGE 0
   .cinit: {} > FLASH PAGE 0
   .switch:{} > FLASH PAGE 0 
   
   .const: {} > B0B1  PAGE 1
   .data:{}   > B0B1  PAGE 1                 /* CONSTANTS                           */
   .stack: {} > SARAM PAGE 1                  /* SYSTEM STACK                        */
   .sysmem:{} > SARAM PAGE 1                  /* DYNAMIC MEMORY - DELETE IF NOT USED */
   .bss:   {} > SARAM PAGE 1                  /* VARIABLES                           */
   .const: {} > SARAM PAGE 1

}
 /*
 -c                                        
-stack 0x400                            
-heap  0x400                            
-l rts2xx.lib 
  
MEMORY
{
	PAGE 0 :
		VECS:  origin = 00000h, length = 00040h 
  	   
	    CODE:  origin = 0x8000, length = 0x800
	PAGE 1 :

		DSRAM  : origin = 0x60 , length =  0x4000
}

                                       
SECTIONS
{

.text     :  {}> CODE      PAGE 0
.cinit    :  {}> CODE      PAGE 0
.switch   :  {}> CODE      PAGE 0 

.bss      :  {}> DSRAM       PAGE 1
.data     :  {}> DSRAM       PAGE 1
.const    :  {}> DSRAM       PAGE 1
.stack    :  {}> DSRAM       PAGE 1
.sysmem   :  {}> DSRAM       PAGE 1
}

*/