#define PHY_B_AS_PDF		(1<<7)	/* Bit  7:	Parallel Detect. Fault */#define PHY_B_AS_RF			(1<<6)	/* Bit  6:	Remote Fault */#define PHY_B_AS_ANP_R		(1<<5)	/* Bit  5:	AN Page Received */#define PHY_B_AS_LP_ANAB	(1<<4)	/* Bit  4:	LP AN Ability */#define PHY_B_AS_LP_NPAB	(1<<3)	/* Bit  3:	LP Next Page Ability */#define PHY_B_AS_LS			(1<<2)	/* Bit  2:	Link Status */#define PHY_B_AS_PRR		(1<<1)	/* Bit  1:	Pause Resolution-Rx */#define PHY_B_AS_PRT		(1<<0)	/* Bit  0:	Pause Resolution-Tx */#define PHY_B_AS_PAUSE_MSK	(PHY_B_AS_PRR | PHY_B_AS_PRT)/*****  PHY_BCOM_INT_STAT	16 bit r/o	Interrupt Status Reg *****//*****  PHY_BCOM_INT_MASK	16 bit r/w	Interrupt Mask Reg *****/									/* Bit 15:	reserved */#define PHY_B_IS_PSE		(1<<14)	/* Bit 14:	Pair Swap Error */#define PHY_B_IS_MDXI_SC	(1<<13)	/* Bit 13:	MDIX Status Change */#define PHY_B_IS_HCT		(1<<12)	/* Bit 12:	counter above 32k */#define PHY_B_IS_LCT		(1<<11)	/* Bit 11:	counter above 128 */#define PHY_B_IS_AN_PR		(1<<10)	/* Bit 10:	Page Received */#define PHY_B_IS_NO_HDCL	(1<<9)	/* Bit  9:	No HCD Link */#define PHY_B_IS_NO_HDC		(1<<8)	/* Bit  8:	No HCD */#define PHY_B_IS_NEG_USHDC	(1<<7)	/* Bit  7:	Negotiated Unsup. HCD */#define PHY_B_IS_SCR_S_ER	(1<<6)	/* Bit  6:	Scrambler Sync Error */#define PHY_B_IS_RRS_CHANGE	(1<<5)	/* Bit  5:	Remote Rx Stat Change */#define PHY_B_IS_LRS_CHANGE	(1<<4)	/* Bit  4:	Local Rx Stat Change */#define PHY_B_IS_DUP_CHANGE	(1<<3)	/* Bit  3:	Duplex Mode Change */#define PHY_B_IS_LSP_CHANGE	(1<<2)	/* Bit  2:	Link Speed Change */#define PHY_B_IS_LST_CHANGE	(1<<1)	/* Bit  1:	Link Status Changed */#define PHY_B_IS_CRC_ER		(1<<0)	/* Bit  0:	CRC Error */#define PHY_B_DEF_MSK	(~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */#define PHY_B_P_NO_PAUSE	(0<<10)	/* Bit 11..10:	no Pause Mode */#define PHY_B_P_SYM_MD		(1<<10)	/* Bit 11..10:	symmetric Pause Mode */#define PHY_B_P_ASYM_MD		(2<<10)	/* Bit 11..10:	asymmetric Pause Mode */#define PHY_B_P_BOTH_MD		(3<<10)	/* Bit 11..10:	both Pause Mode *//* * Resolved Duplex mode and Capabilities (Aux Status Summary Reg) */#define PHY_B_RES_1000FD	(7<<8)	/* Bit 10..8:	1000Base-T Full Dup. */#define PHY_B_RES_1000HD	(6<<8)	/* Bit 10..8:	1000Base-T Half Dup. *//* others: 100/10: invalid for us *//* * Level One-Specific *//*****  PHY_LONE_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/#define PHY_L_1000C_TEST	(7<<13)	/* Bit 15..13:	Test Modes */#define PHY_L_1000C_MSE		(1<<12)	/* Bit 12:	Master/Slave Enable */#define PHY_L_1000C_MSC		(1<<11)	/* Bit 11:	M/S Configuration */#define PHY_L_1000C_RD		(1<<10)	/* Bit 10:	Repeater/DTE */#define PHY_L_1000C_AFD		(1<<9)	/* Bit  9:	Advertise Full Duplex */#define PHY_L_1000C_AHD		(1<<8)	/* Bit  8:	Advertise Half Duplex */									/* Bit  7..0:	reserved *//*****  PHY_LONE_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/#define PHY_L_1000S_MSF		(1<<15)	/* Bit 15:	Master/Slave Fault */#define PHY_L_1000S_MSR		(1<<14)	/* Bit 14:	Master/Slave Result */#define PHY_L_1000S_LRS		(1<<13)	/* Bit 13:	Local Receiver Status */#define PHY_L_1000S_RRS		(1<<12)	/* Bit 12:	Remote Receiver Status*/#define PHY_L_1000S_LP_FD	(1<<11)	/* Bit 11:	Link Partner can FD */#define PHY_L_1000S_LP_HD	(1<<10)	/* Bit 10:	Link Partner can HD */									/* Bit  9..8:	reserved */#define PHY_B_1000S_IEC		0xff	/* Bit  7..0:	Idle Error Count *//*****  PHY_LONE_EXT_STAT	16 bit r/o	Extended Status Register *****/#define PHY_L_ES_X_FD_CAP	(1<<15)	/* Bit 15:	1000Base-X FD capable */#define PHY_L_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */#define PHY_L_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */#define PHY_L_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */									/* Bit 11..0:	reserved *//*****  PHY_LONE_PORT_CFG	16 bit r/w	Port Configuration Reg *****/#define PHY_L_PC_REP_MODE	(1<<15)	/* Bit 15:	Repeater Mode */									/* Bit 14:	reserved */#define PHY_L_PC_TX_DIS		(1<<13)	/* Bit 13:	Tx output Disabled */#define PHY_L_PC_BY_SCR		(1<<12)	/* Bit 12:	Bypass Scrambler */#define PHY_L_PC_BY_45		(1<<11)	/* Bit 11:	Bypass 4B5B-Decoder */#define PHY_L_PC_JAB_DIS	(1<<10)	/* Bit 10:	Jabber Disabled */#define PHY_L_PC_SQE		(1<<9)	/* Bit  9:	Enable Heartbeat */#define PHY_L_PC_TP_LOOP	(1<<8)	/* Bit  8:	TP Loopback */#define PHY_L_PC_SSS		(1<<7)	/* Bit  7:	Smart Speed Selection */#define PHY_L_PC_FIFO_SIZE	(1<<6)	/* Bit  6:	FIFO Size */#define PHY_L_PC_PRE_EN		(1<<5)	/* Bit  5:	Preamble Enable */#define PHY_L_PC_CIM		(1<<4)	/* Bit  4:	Carrier Integrity Mon */#define PHY_L_PC_10_SER		(1<<3)	/* Bit  3:	Use Serial Output */#define PHY_L_PC_ANISOL		(1<<2)	/* Bit  2:	Unisolate Port */#define PHY_L_PC_TEN_BIT	(1<<1)	/* Bit  1:	10bit iface mode on */#define PHY_L_PC_ALTCLOCK	(1<<0)	/* Bit  0: (ro)	ALTCLOCK Mode on *//*****  PHY_LONE_Q_STAT		16 bit r/o	Quick Status Reg *****/#define PHY_L_QS_D_RATE		(3<<14)	/* Bit 15..14:	Data Rate */#define PHY_L_QS_TX_STAT	(1<<13)	/* Bit 13:	Transmitting */#define PHY_L_QS_RX_STAT	(1<<12)	/* Bit 12:	Receiving */#define PHY_L_QS_COL_STAT	(1<<11)	/* Bit 11:	Collision */#define PHY_L_QS_L_STAT		(1<<10)	/* Bit 10:	Link is up */#define PHY_L_QS_DUP_MOD	(1<<9)	/* Bit  9:	Full/Half Duplex */#define PHY_L_QS_AN			(1<<8)	/* Bit  8:	AutoNeg is On */#define PHY_L_QS_AN_C		(1<<7)	/* Bit  7:	AN is Complete */#define PHY_L_QS_LLE		(7<<4)	/* Bit  6:	Line Length Estim. */#define PHY_L_QS_PAUSE		(1<<3)	/* Bit  3:	LP advertised Pause */#define PHY_L_QS_AS_PAUSE	(1<<2)	/* Bit  2:	LP adv. asym. Pause */#define PHY_L_QS_ISOLATE	(1<<1)	/* Bit  1:	CIM Isolated */#define PHY_L_QS_EVENT		(1<<0)	/* Bit  0:	Event has occurred *//*****  PHY_LONE_INT_ENAB	16 bit r/w	Interrupt Enable Reg *****//*****  PHY_LONE_INT_STAT	16 bit r/o	Interrupt Status Reg *****/									/* Bit 15..14:	reserved */#define PHY_L_IS_AN_F		(1<<13)	/* Bit 13:	Auto-Negotiation fault */									/* Bit 12:	not described */#define PHY_L_IS_CROSS		(1<<11)	/* Bit 11:	Crossover used */#define PHY_L_IS_POL		(1<<10)	/* Bit 10:	Polarity correct. used*/#define PHY_L_IS_SS			(1<<9)	/* Bit  9:	Smart Speed Downgrade*/#define PHY_L_IS_CFULL		(1<<8)	/* Bit  8:	Counter Full */#define PHY_L_IS_AN_C		(1<<7)	/* Bit  7:	AutoNeg Complete */#define PHY_L_IS_SPEED		(1<<6)	/* Bit  6:	Speed Changed */#define PHY_L_IS_DUP		(1<<5)	/* Bit  5:	Duplex Changed */#define PHY_L_IS_LS			(1<<4)	/* Bit  4:	Link Status Changed */#define PHY_L_IS_ISOL		(1<<3)	/* Bit  3:	Isolate Occured */#define PHY_L_IS_MDINT		(1<<2)	/* Bit  2: (ro)	STAT: MII Int Pending */#define PHY_L_IS_INTEN		(1<<1)	/* Bit  1:	ENAB: Enable IRQs */#define PHY_L_IS_FORCE		(1<<0)	/* Bit  0:	ENAB: Force Interrupt *//* int. mask */#define PHY_L_DEF_MSK		(PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)/*****  PHY_LONE_LED_CFG	16 bit r/w	LED Configuration Reg *****/#define PHY_L_LC_LEDC		(3<<14)	/* Bit 15..14:	Col/Blink/On/Off */#define PHY_L_LC_LEDR		(3<<12)	/* Bit 13..12:	Rx/Blink/On/Off */#define PHY_L_LC_LEDT		(3<<10)	/* Bit 11..10:	Tx/Blink/On/Off */#define PHY_L_LC_LEDG		(3<<8)	/* Bit  9..8:	Giga/Blink/On/Off */#define PHY_L_LC_LEDS		(3<<6)	/* Bit  7..6:	10-100/Blink/On/Off */#define PHY_L_LC_LEDL		(3<<4)	/* Bit  5..4:	Link/Blink/On/Off */#define PHY_L_LC_LEDF		(3<<2)	/* Bit  3..2:	Duplex/Blink/On/Off */#define PHY_L_LC_PSTRECH	(1<<1)	/* Bit  1:	Strech LED Pulses */#define PHY_L_LC_FREQ		(1<<0)	/* Bit  0:	30/100 ms *//*****  PHY_LONE_PORT_CTRL	16 bit r/w	Port Control Reg *****/#define PHY_L_PC_TX_TCLK	(1<<15)	/* Bit 15:	Enable TX_TCLK */									/* Bit 14:	reserved */#define PHY_L_PC_ALT_NP		(1<<13)	/* Bit 14:	Alternate Next Page */#define PHY_L_PC_GMII_ALT	(1<<12)	/* Bit 13:	Alternate GMII driver */									/* Bit 11:	reserved */#define PHY_L_PC_TEN_CRS	(1<<10)	/* Bit 10:	Extend CRS*/									/* Bit  9..0:	not described *//*****  PHY_LONE_CIM		16 bit r/o	CIM Reg *****/#define PHY_L_CIM_ISOL		(255<<8)/* Bit 15..8:	Isolate Count */#define PHY_L_CIM_FALSE_CAR	(255<<0)/* Bit  7..0:	False Carrier Count *//* * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding */#define PHY_L_P_NO_PAUSE	(0<<10)	/* Bit 11..10:	no Pause Mode */#define PHY_L_P_SYM_MD		(1<<10)	/* Bit 11..10:	symmetric Pause Mode */#define PHY_L_P_ASYM_MD		(2<<10)	/* Bit 11..10:	asymmetric Pause Mode */#define PHY_L_P_BOTH_MD		(3<<10)	/* Bit 11..10:	both Pause Mode *//* * National-Specific *//*****  PHY_NAT_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/#define PHY_N_1000C_TEST	(7<<13)	/* Bit 15..13:	Test Modes */#define PHY_N_1000C_MSE		(1<<12)	/* Bit 12:	Master/Slave Enable */#define PHY_N_1000C_MSC		(1<<11)	/* Bit 11:	M/S Configuration */#define PHY_N_1000C_RD		(1<<10)	/* Bit 10:	Repeater/DTE */#define PHY_N_1000C_AFD		(1<<9)	/* Bit  9:	Advertise Full Duplex */#define PHY_N_1000C_AHD		(1<<8)	/* Bit  8:	Advertise Half Duplex */#define PHY_N_1000C_APC		(1<<7)	/* Bit  7:	Asymmetric Pause Cap. */									/* Bit  6..0:	reserved *//*****  PHY_NAT_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/#define PHY_N_1000S_MSF		(1<<15)	/* Bit 15:	Master/Slave Fault */#define PHY_N_1000S_MSR		(1<<14)	/* Bit 14:	Master/Slave Result */#define PHY_N_1000S_LRS		(1<<13)	/* Bit 13:	Local Receiver Status */#define PHY_N_1000S_RRS		(1<<12)	/* Bit 12:	Remote Receiver Status*/#define PHY_N_1000S_LP_FD	(1<<11)	/* Bit 11:	Link Partner can FD */#define PHY_N_1000S_LP_HD	(1<<10)	/* Bit 10:	Link Partner can HD */#define PHY_N_1000C_LP_APC	(1<<9)	/* Bit  9:	LP Asym. Pause Cap. */									/* Bit  8:	reserved */#define PHY_N_1000S_IEC		0xff	/* Bit  7..0:	Idle Error Count *//*****  PHY_NAT_EXT_STAT	16 bit r/o	Extended Status Register *****/#define PHY_N_ES_X_FD_CAP	(1<<15)	/* Bit 15:	1000Base-X FD capable */#define PHY_N_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */#define PHY_N_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */#define PHY_N_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */									/* Bit 11..0:	reserved *//* todo: those are still missing *//*****  PHY_NAT_EXT_CTRL1	16 bit r/o	Extended Control Reg1 *****//*****  PHY_NAT_Q_STAT1		16 bit r/o	Quick Status Reg1 *****//*****  PHY_NAT_10B_OP		16 bit r/o	10Base-T Operations Reg *****//*****  PHY_NAT_EXT_CTRL2	16 bit r/o	Extended Control Reg1 *****//*****  PHY_NAT_Q_STAT2		16 bit r/o	Quick Status Reg2 *****//*****  PHY_NAT_PHY_ADDR	16 bit r/o	PHY Address Register *****//* * Marvell-Specific *//*****  PHY_MARV_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****//*****  PHY_MARV_AUNE_LP	16 bit r/w	Link Part Ability Reg *****/#define PHY_M_AN_NXT_PG		BIT_15	/* Request Next Page */#define PHY_M_AN_ACK		BIT_14	/* (ro)	Acknowledge Received */#define PHY_M_AN_RF			BIT_13	/* Remote Fault */									/* Bit 12:	reserved */#define PHY_M_AN_ASP		BIT_11	/* Asymmetric Pause */#define PHY_M_AN_PC			BIT_10	/* MAC Pause implemented */#define PHY_M_AN_100_FD		BIT_8	/* Advertise 100Base-TX Full Duplex */#define PHY_M_AN_100_HD		BIT_7	/* Advertise 100Base-TX Half Duplex */#define PHY_M_AN_10_FD		BIT_6	/* Advertise 10Base-TX Full Duplex */#define PHY_M_AN_10_HD		BIT_5	/* Advertise 10Base-TX Half Duplex *//* special defines for FIBER (88E1011S only) */#define PHY_M_AN_ASP_X		BIT_8	/* Asymmetric Pause */#define PHY_M_AN_PC_X		BIT_7	/* MAC Pause implemented */#define PHY_M_AN_1000X_AHD	BIT_6	/* Advertise 10000Base-X Half Duplex */#define PHY_M_AN_1000X_AFD	BIT_5	/* Advertise 10000Base-X Full Duplex *//* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */#define PHY_M_P_NO_PAUSE_X	(0<<7)	/* Bit  8.. 7:	no Pause Mode */#define PHY_M_P_SYM_MD_X	(1<<7)	/* Bit  8.. 7:	symmetric Pause Mode */#define PHY_M_P_ASYM_MD_X	(2<<7)	/* Bit  8.. 7:	asymmetric Pause Mode */#define PHY_M_P_BOTH_MD_X	(3<<7)	/* Bit  8.. 7:	both Pause Mode *//*****  PHY_MARV_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/#define PHY_M_1000C_TEST	(7<<13)	/* Bit 15..13:	Test Modes */#define PHY_M_1000C_MSE		(1<<12)	/* Bit 12:	Manual Master/Slave Enable */#define PHY_M_1000C_MSC		(1<<11)	/* Bit 11:	M/S Configuration (1=Master) */#define PHY_M_1000C_MPD		(1<<10)	/* Bit 10:	Multi-Port Device */#define PHY_M_1000C_AFD		(1<<9)	/* Bit  9:	Advertise Full Duplex */#define PHY_M_1000C_AHD		(1<<8)	/* Bit  8:	Advertise Half Duplex */									/* Bit  7..0:	reserved *//*****  PHY_MARV_PHY_CTRL	16 bit r/w	PHY Specific Ctrl Reg *****/#define PHY_M_PC_TX_FFD_MSK	(3<<14)	/* Bit 15..14:	Tx FIFO Depth Mask */#define PHY_M_PC_RX_FFD_MSK	(3<<12)	/* Bit 13..12:	Rx FIFO Depth Mask */#define PHY_M_PC_ASS_CRS_TX	(1<<11)	/* Bit 11:	Assert CRS on Transmit */#define PHY_M_PC_FL_GOOD	(1<<10)	/* Bit 10:	Force Link Good */#define PHY_M_PC_EN_DET_MSK	(3<<8)	/* Bit  9.. 8:	Energy Detect Mask */#define PHY_M_PC_ENA_EXT_D	(1<<7)	/* Bit  7:	Enable Ext. Distance (10BT) */#define PHY_M_PC_MDIX_MSK	(3<<5)	/* Bit  6.. 5:	MDI/MDIX Config. Mask */#define PHY_M_PC_DIS_125CLK	(1<<4)	/* Bit  4:	Disable 125 CLK */#define PHY_M_PC_MAC_POW_UP	(1<<3)	/* Bit  3:	MAC Power up */#define PHY_M_PC_SQE_T_ENA	(1<<2)	/* Bit  2:	SQE Test Enabled */#define PHY_M_PC_POL_R_DIS	(1<<1)	/* Bit  1:	Polarity Reversal Disabled */#define PHY_M_PC_DIS_JABBER	(1<<0)	/* Bit  0:	Disable Jabber */#define PHY_M_PC_MDI_XMODE(x)	SHIFT5(x)#define PHY_M_PC_MAN_MDI	0    	/* 00 = Manual MDI configuration */#define PHY_M_PC_MAN_MDIX	1		/* 01 = Manual MDIX configuration */#define PHY_M_PC_ENA_AUTO	3		/* 11 = Enable Automatic Crossover *//*****  PHY_MARV_PHY_STAT	16 bit r/o	PHY Specific Status Reg *****/#define PHY_M_PS_SPEED_MSK	(3<<14)	/* Bit 15..14:	Speed Mask */#define PHY_M_PS_SPEED_1000	(1<<15)	/*       10 = 1000 Mbps */#define PHY_M_PS_SPEED_100	(1<<14)	/*       01 =  100 Mbps */#define PHY_M_PS_SPEED_10	0		/*       00 =   10 Mbps */#define PHY_M_PS_FULL_DUP	(1<<13)	/* Bit 13:	Full Duplex */#define PHY_M_PS_PAGE_REC	(1<<12)	/* Bit 12:	Page Received */#define PHY_M_PS_SPDUP_RES	(1<<11)	/* Bit 11:	Speed & Duplex Resolved *