/* * (C) Copyright 2003 * Ingo Assmus <ingo.assmus@keymile.com> * * based on - Driver for MV64360X ethernet ports * Copyright (C) 2002 rabeeh@galileo.co.il * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA *//* * mv_eth.h - header file for the polled mode GT ethernet driver */#ifndef __DB64360_ETH_H__#define __DB64360_ETH_H__#include <asm/types.h>#include <asm/io.h>#include <asm/byteorder.h>#include <common.h>#include <net.h>#include "mv_regs.h"#include "../../Marvell/common/ppc_error_no.h"/******************************************************************************************************************************************************************************************************************************  The first part is the high level driver of the gigE ethernet ports.	 ******************************************************************************************************************************************************************************************************************************/#ifndef TRUE#define TRUE 1#endif#ifndef FALSE#define FALSE 0#endif/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */#ifndef MAX_SKB_FRAGS#define MAX_SKB_FRAGS 0#endif/* Port attributes *//*#define MAX_RX_QUEUE_NUM	8*//*#define MAX_TX_QUEUE_NUM	8*/#define MAX_RX_QUEUE_NUM	1#define MAX_TX_QUEUE_NUM	1/* Use one TX queue and one RX queue */#define MV64360_TX_QUEUE_NUM 1#define MV64360_RX_QUEUE_NUM 1/* * Number of RX / TX descriptors on RX / TX rings. * Note that allocating RX descriptors is done by allocating the RX * ring AND a preallocated RX buffers (skb's) for each descriptor. * The TX descriptors only allocates the TX descriptors ring, * with no pre allocated TX buffers (skb's are allocated by higher layers. *//* Default TX ring size is 10 descriptors */#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE#else#define MV64360_TX_QUEUE_SIZE 4#endif/* Default RX ring size is 4 descriptors */#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE#else#define MV64360_RX_QUEUE_SIZE 4#endif#ifdef CONFIG_RX_BUFFER_SIZE#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE#else#define MV64360_RX_BUFFER_SIZE 1600#endif#ifdef CONFIG_TX_BUFFER_SIZE#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE#else#define MV64360_TX_BUFFER_SIZE 1600#endif/* *	Network device statistics. Akin to the 2.0 ether stats but *	with byte counters. */struct net_device_stats{	unsigned long	rx_packets;		/* total packets received	*/	unsigned long	tx_packets;		/* total packets transmitted	*/	unsigned long	rx_bytes;		/* total bytes received		*/	unsigned long	tx_bytes;		/* total bytes transmitted	*/	unsigned long	rx_errors;		/* bad packets received		*/	unsigned long	tx_errors;		/* packet transmit problems	*/	unsigned long	rx_dropped;		/* no space in linux buffers	*/	unsigned long	tx_dropped;		/* no space available in linux	*/	unsigned long	multicast;		/* multicast packets received	*/	unsigned long	collisions;	/* detailed rx_errors: */	unsigned long	rx_length_errors;	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/	unsigned long	rx_missed_errors;	/* receiver missed packet	*/	/* detailed tx_errors */	unsigned long	tx_aborted_errors;	unsigned long	tx_carrier_errors;	unsigned long	tx_fifo_errors;	unsigned long	tx_heartbeat_errors;	unsigned long	tx_window_errors;	/* for cslip etc */	unsigned long	rx_compressed;	unsigned long	tx_compressed;};/* Private data structure used for ethernet device */struct mv64360_eth_priv {    unsigned int port_num;    struct net_device_stats *stats;/* to buffer area aligned */    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */    /* Size of Tx Ring per queue */    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];    /* Size of Rx Ring per queue */    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];    /* Magic Number for Ethernet running */    unsigned int eth_running;};int mv64360_eth_init (struct eth_device *dev);int mv64360_eth_stop (struct eth_device *dev);int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);/*	return db64360_eth0_poll(); */int mv64360_eth_open (struct eth_device *dev);/******************************************************************************************************************************************************************************************************************************  The second part is the low level driver of the gigE ethernet ports.	 ******************************************************************************************************************************************************************************************************************************//******************************************************************************** * Header File for : MV-643xx network interface header * * DESCRIPTION: *	 This header file contains macros typedefs and function declaration for *	 the Marvell Gig Bit Ethernet Controller. * * DEPENDENCIES: *	 None. * *******************************************************************************/#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY#ifdef CONFIG_MV64360_SRAM_CACHEABLE/* In case SRAM is cacheable but not cache coherent */#define D_CACHE_FLUSH_LINE(addr, offset)       \{		    \  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \}#else/* In case SRAM is cache coherent or non-cacheable */#define D_CACHE_FLUSH_LINE(addr, offset) ;#endif#else#ifdef CONFIG_NOT_COHERENT_CACHE/* In case of descriptors on DDR but not cache coherent */#define D_CACHE_FLUSH_LINE(addr, offset)       \{		    \  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \}#else/* In case of descriptors on DDR and cache coherent */#define D_CACHE_FLUSH_LINE(addr, offset) ;#endif /* CONFIG_NOT_COHERENT_CACHE */#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */#define CPU_PIPE_FLUSH		   \{		  \  __asm__ __volatile__ ("eieio");	  \}/* defines  *//* Default port configuration value */#define PORT_CONFIG_VALUE			\	     ETH_UNICAST_NORMAL_MODE		|   \	     ETH_DEFAULT_RX_QUEUE_0		|   \	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \	     ETH_RECEIVE_BC_IF_IP		|   \	     ETH_RECEIVE_BC_IF_ARP		|   \	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \	     ETH_DEFAULT_RX_BPDU_QUEUE_0/* Default port extend configuration value */#define PORT_CONFIG_EXTEND_VALUE		\	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \	     ETH_PARTITION_DISABLE/* Default sdma control value */#ifdef CONFIG_NOT_COHERENT_CACHE#define PORT_SDMA_CONFIG_VALUE				\			 ETH_RX_BURST_SIZE_16_64BIT	|	\			 GT_ETH_IPG_INT_RX(0)			|	\			 ETH_TX_BURST_SIZE_16_64BIT;#else#define PORT_SDMA_CONFIG_VALUE			\			 ETH_RX_BURST_SIZE_4_64BIT	|	\			 GT_ETH_IPG_INT_RX(0)			|	\			 ETH_TX_BURST_SIZE_4_64BIT;#endif#define GT_ETH_IPG_INT_RX(value)		\	    ((value & 0x3fff) << 8)/* Default port serial control value */#define PORT_SERIAL_CONTROL_VALUE			    \			ETH_FORCE_LINK_PASS			|	\			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\			ETH_FORCE_BP_MODE_NO_JAM		|	\			BIT9					|	\			ETH_DO_NOT_FORCE_LINK_FAIL		|	\			ETH_RETRANSMIT_16_ETTEMPTS		|	\			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\			ETH_DTE_ADV_0				|	\			ETH_DISABLE_AUTO_NEG_BYPASS		|	\			ETH_AUTO_NEG_NO_CHANGE			|	\			ETH_MAX_RX_PACKET_1552BYTE		|	\			ETH_CLR_EXT_LOOPBACK			|	\			ETH_SET_FULL_DUPLEX_MODE		|	\			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;#define RX_BUFFER_MAX_SIZE  0xFFFF#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */#define RX_BUFFER_MIN_SIZE  0x8#define TX_BUFFER_MIN_SIZE  0x8/* Tx WRR confoguration macros */#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     *//* MAC accepet/reject macros */#define ACCEPT_MAC_ADDR	    0#define REJECT_MAC_ADDR	    1/* Size of a Tx/Rx descriptor used in chain list data structure */#define RX_DESC_ALIGNED_SIZE		0x20#define TX_DESC_ALIGNED_SIZE		0x20/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */#define TX_BUF_OFFSET_IN_DESC	    0x18/* Buffer offset from buffer pointer */#define RX_BUF_OFFSET				0x2/* Gap define */#define ETH_BAR_GAP					0x8#define ETH_SIZE_REG_GAP				0x8#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4#define ETH_PORT_ACCESS_CTRL_GAP			0x4/* Gigabit Ethernet Unit Global Registers *//* MIB Counters register definitions */#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c#define ETH_MIB_FRAMES_64_OCTETS	   0x20#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c#define ETH_MIB_GOOD_FRAMES_SENT	   0x40#define ETH_MIB_EXCESSIVE_COLLISION	   0x44#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50#define ETH_MIB_FC_SENT			   0x54#define ETH_MIB_GOOD_FC_RECEIVED	   0x58#define ETH_MIB_BAD_FC_RECEIVED		   0x5c#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64#define ETH_MIB_OVERSIZE_RECEIVED	   0x68#define ETH_MIB_JABBER_RECEIVED		   0x6c#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70#define ETH_MIB_BAD_CRC_EVENT		   0x74#define ETH_MIB_COLLISION		   0x78#define ETH_MIB_LATE_COLLISION		   0x7c/* Port serial status reg (PSR) */#define ETH_INTERFACE_GMII_MII				0#define ETH_INTERFACE_PCM				BIT0#define ETH_LINK_IS_DOWN				0#define ETH_LINK_IS_UP					BIT1#define ETH_PORT_AT_HALF_DUPLEX				0#define ETH_PORT_AT_FULL_DUPLEX				BIT2#define ETH_RX_FLOW_CTRL_DISABLED			0#define ETH_RX_FLOW_CTRL_ENBALED			BIT3#define ETH_GMII_SPEED_100_10				0#define ETH_GMII_SPEED_1000				BIT4#define ETH_MII_SPEED_10				0#define ETH_MII_SPEED_100				BIT5#define ETH_NO_TX					0#define ETH_TX_IN_PROGRESS				BIT7#define ETH_BYPASS_NO_ACTIVE				0#define ETH_BYPASS_ACTIVE				BIT8#define ETH_PORT_NOT_AT_PARTITION_STATE			0#define ETH_PORT_AT_PARTITION_STATE			BIT9#define ETH_PORT_TX_FIFO_NOT_EMPTY			0#define ETH_PORT_TX_FIFO_EMPTY				BIT10/* These macros describes the Port configuration reg (Px_cR) bits */#define ETH_UNICAST_NORMAL_MODE				0#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0#define ETH_DEFAULT_RX_QUEUE_0				0#define ETH_DEFAULT_RX_QUEUE_1				BIT1#define ETH_DEFAULT_RX_QUEUE_2				BIT2#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)#define ETH_DEFAULT_RX_QUEUE_4				BIT3#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)#define ETH_DEFAULT_RX_ARP_QUEUE_0			0#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7#define ETH_RECEIVE_BC_IF_IP				0#define ETH_REJECT_BC_IF_IP				BIT8#define ETH_RECEIVE_BC_IF_ARP				0#define ETH_REJECT_BC_IF_ARP				BIT9#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12#define ETH_CAPTURE_TCP_FRAMES_DIS			0#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14#define ETH_CAPTURE_UDP_FRAMES_DIS			0#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15#define ETH_DEFAULT_RX_TCP_QUEUE_0			0#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)#define ETH_DEFAULT_RX_UDP_QUEUE_0			0#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0