#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)/* These macros describes the Port configuration extend reg (Px_cXR) bits*/#define ETH_CLASSIFY_EN					BIT0#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1#define ETH_PARTITION_DISABLE				0#define ETH_PARTITION_ENABLE				BIT2/* Tx/Rx queue command reg (RQCR/TQCR)*/#define ETH_QUEUE_0_ENABLE				BIT0#define ETH_QUEUE_1_ENABLE				BIT1#define ETH_QUEUE_2_ENABLE				BIT2#define ETH_QUEUE_3_ENABLE				BIT3#define ETH_QUEUE_4_ENABLE				BIT4#define ETH_QUEUE_5_ENABLE				BIT5#define ETH_QUEUE_6_ENABLE				BIT6#define ETH_QUEUE_7_ENABLE				BIT7#define ETH_QUEUE_0_DISABLE				BIT8#define ETH_QUEUE_1_DISABLE				BIT9#define ETH_QUEUE_2_DISABLE				BIT10#define ETH_QUEUE_3_DISABLE				BIT11#define ETH_QUEUE_4_DISABLE				BIT12#define ETH_QUEUE_5_DISABLE				BIT13#define ETH_QUEUE_6_DISABLE				BIT14#define ETH_QUEUE_7_DISABLE				BIT15/* These macros describes the Port Sdma configuration reg (SDCR) bits */#define ETH_RIFB					BIT0#define ETH_RX_BURST_SIZE_1_64BIT			0#define ETH_RX_BURST_SIZE_2_64BIT			BIT1#define ETH_RX_BURST_SIZE_4_64BIT			BIT2#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)#define ETH_RX_BURST_SIZE_16_64BIT			BIT3#define ETH_BLM_RX_NO_SWAP				BIT4#define ETH_BLM_RX_BYTE_SWAP				0#define ETH_BLM_TX_NO_SWAP				BIT5#define ETH_BLM_TX_BYTE_SWAP				0#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6#define ETH_DESCRIPTORS_NO_SWAP				0#define ETH_TX_BURST_SIZE_1_64BIT			0#define ETH_TX_BURST_SIZE_2_64BIT			BIT22#define ETH_TX_BURST_SIZE_4_64BIT			BIT23#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)#define ETH_TX_BURST_SIZE_16_64BIT			BIT24/* These macros describes the Port serial control reg (PSCR) bits */#define ETH_SERIAL_PORT_DISABLE				0#define ETH_SERIAL_PORT_ENABLE				BIT0#define ETH_FORCE_LINK_PASS				BIT1#define ETH_DO_NOT_FORCE_LINK_PASS			0#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3#define ETH_ADV_NO_FLOW_CTRL				0#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5#define ETH_FORCE_BP_MODE_NO_JAM			0#define ETH_FORCE_BP_MODE_JAM_TX			BIT7#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8#define ETH_FORCE_LINK_FAIL				0#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10#define ETH_RETRANSMIT_16_ETTEMPTS			0#define ETH_RETRANSMIT_FOREVER				BIT11#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0#define ETH_DTE_ADV_0					0#define ETH_DTE_ADV_1					BIT14#define ETH_DISABLE_AUTO_NEG_BYPASS			0#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15#define ETH_AUTO_NEG_NO_CHANGE				0#define ETH_RESTART_AUTO_NEG				BIT16#define ETH_MAX_RX_PACKET_1518BYTE			0#define ETH_MAX_RX_PACKET_1522BYTE			BIT17#define ETH_MAX_RX_PACKET_1552BYTE			BIT18#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)#define ETH_MAX_RX_PACKET_9192BYTE			BIT19#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)#define ETH_SET_EXT_LOOPBACK				BIT20#define ETH_CLR_EXT_LOOPBACK				0#define ETH_SET_FULL_DUPLEX_MODE			BIT21#define ETH_SET_HALF_DUPLEX_MODE			0#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0#define ETH_SET_GMII_SPEED_TO_10_100			0#define ETH_SET_GMII_SPEED_TO_1000			BIT23#define ETH_SET_MII_SPEED_TO_10				0#define ETH_SET_MII_SPEED_TO_100			BIT24/* SMI reg */#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*//* SDMA command status fields macros *//* Tx & Rx descriptors status */#define ETH_ERROR_SUMMARY		    (BIT0)/* Tx & Rx descriptors command */#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)/* Tx descriptors status */#define ETH_LC_ERROR			    (0	  )#define ETH_UR_ERROR			    (BIT1 )#define ETH_RL_ERROR			    (BIT2 )#define ETH_LLC_SNAP_FORMAT		    (BIT9 )/* Rx descriptors status */#define ETH_CRC_ERROR			    (0	  )#define ETH_OVERRUN_ERROR		    (BIT1 )#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))#define ETH_VLAN_TAGGED			    (BIT19)#define ETH_BPDU_FRAME			    (BIT20)#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)#define ETH_OTHER_FRAME_TYPE		    (BIT22)#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)#define ETH_FRAME_HEADER_OK		    (BIT25)#define ETH_RX_LAST_DESC		    (BIT26)#define ETH_RX_FIRST_DESC		    (BIT27)#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)/* Rx descriptors byte count */#define ETH_FRAME_FRAGMENTED		    (BIT2)/* Tx descriptors command */#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)#define ETH_FRAME_SET_TO_VLAN		    (BIT15)#define ETH_TCP_FRAME			    (0	  )#define ETH_UDP_FRAME			    (BIT16)#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)#define ETH_ZERO_PADDING		    (BIT19)#define ETH_TX_LAST_DESC		    (BIT20)#define ETH_TX_FIRST_DESC		    (BIT21)#define ETH_GEN_CRC			    (BIT22)#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)#define ETH_AUTO_MODE			    (BIT30)/* Address decode parameters *//* Ethernet Base Address Register bits */#define EBAR_TARGET_DRAM					0x00000000#define EBAR_TARGET_DEVICE					0x00000001#define EBAR_TARGET_CBS						0x00000002#define EBAR_TARGET_PCI0					0x00000003#define EBAR_TARGET_PCI1					0x00000004#define EBAR_TARGET_CUNIT					0x00000005#define EBAR_TARGET_AUNIT					0x00000006#define EBAR_TARGET_GUNIT					0x00000007/* Window attributes */#define EBAR_ATTR_DRAM_CS0					0x00000E00#define EBAR_ATTR_DRAM_CS1					0x00000D00#define EBAR_ATTR_DRAM_CS2					0x00000B00#define EBAR_ATTR_DRAM_CS3					0x00000700/* DRAM Target interface */#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000/* Device Bus Target interface */#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00/* PCI Target interface */#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000#define EBAR_ATTR_PCI_NO_SWAP				0x00000100#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400#define EBAR_ATTR_PCI_IO_SPACE				0x00000000#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000/* CPU 60x bus or internal SRAM interface */#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100#define EBAR_ATTR_CBS_SRAM					0x00000000#define EBAR_ATTR_CBS_CPU_BUS				0x00000800/* Window access control */#define EWIN_ACCESS_NOT_ALLOWED 0#define EWIN_ACCESS_READ_ONLY	BIT0#define EWIN_ACCESS_FULL	(BIT1 | BIT0)#define EWIN0_ACCESS_MASK		0x0003#define EWIN1_ACCESS_MASK		0x000C#define EWIN2_ACCESS_MASK		0x0030#define EWIN3_ACCESS_MASK		0x00C0/* typedefs */typedef enum _eth_port{    ETH_0 = 0,	ETH_1 = 1,	ETH_2 = 2}ETH_PORT;typedef enum _eth_func_ret_status{    ETH_OK,			/* Returned as expected.		    */    ETH_ERROR,			/* Fundamental error.			    */    ETH_RETRY,			/* Could not process request. Try later.    */    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */    ETH_QUEUE_FULL,		/* Ring resource error.			    */    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */}ETH_FUNC_RET_STATUS;typedef enum _eth_queue{	ETH_Q0 = 0,	ETH_Q1 = 1,	ETH_Q2 = 2,	ETH_Q3 = 3,	ETH_Q4 = 4,	ETH_Q5 = 5,	ETH_Q6 = 6,    ETH_Q7 = 7} ETH_QUEUE;typedef enum _addr_win{	ETH_WIN0,	ETH_WIN1,	ETH_WIN2,	ETH_WIN3,	ETH_WIN4,    ETH_WIN5} ETH_ADDR_WIN;typedef enum _eth_target{	ETH_TARGET_DRAM	 ,	ETH_TARGET_DEVICE,	ETH_TARGET_CBS	 ,	ETH_TARGET_PCI0	 ,	ETH_TARGET_PCI1}ETH_TARGET;typedef struct _eth_rx_desc{	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */	unsigned short	buf_size	   ;	/* Buffer size			    */	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */    unsigned int    return_info ;    /* User resource return information */} ETH_RX_DESC;typedef struct _eth_tx_desc{    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */    unsigned int    return_info ;    /* User resource return information */} ETH_TX_DESC;/* Unified struct for Rx and Tx operations. The user is not required to *//* be familier with neither Tx nor Rx descriptors.			 */typedef struct _pkt_info{	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */    unsigned int    return_info ;    /* User resource return information */} PKT_INFO;typedef struct _eth_win_param{    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */    unsigned short attributes;	/* BAR attributes. See above macros. */    unsigned int base_addr; /* Window base address in unsigned int form */    unsigned int high_addr; /* Window high address in unsigned int form */    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */    bool enable; /* Enable/disable access to the window. */    unsigned short access_ctrl; /* Access ctrl register. see above macros */} ETH_WIN_PARAM;/* Ethernet port specific infomation */typedef struct _eth_port_ctrl{    ETH_PORT  port_num; /* User Ethernet port number */    int port_phy_addr;	/* User phy address of Ethrnet port */    unsigned char port_mac_addr[6]; /* User defined port MAC address. */    unsigned int  port_config; /* User port configuration value */    unsigned int  port_config_extend; /* User port config extend value */    unsigned int  port_sdma_config; /* User port SDMA config value */    unsigned int  port_serial_control; /* User port serial control value */    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */    /* User function to cast virtual address to CPU bus address */    unsigned int  (*port_virt_to_phys)(unsigned int addr);    /* User scratch pad for user specific data structures */    void *port_private;    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */    /* Tx/Rx rings managment indexes fields. For driver use */    /* Next available Rx resource */    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];    /* Returning Rx resource */    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];    /* Next available Tx resource */    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];    /* Returning Tx resource */    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];    /* An extra Tx index to support transmit of multiple buffers per packet */    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];    /* Tx/Rx rings size and base variables fields. For driver use */    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];} ETH_PORT_INFO;/* ethernet.h API list *//* Port operation control routines */static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);static void eth_port_reset(ETH_PORT	eth_port_num);static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);/* Port MAC address routines */static void eth_port_uc_addr_set (ETH_PORT eth_port_num,				  unsigned char *p_addr,				  ETH_QUEUE queue);#if 0	/* FIXME */static void eth_port_mc_addr	(ETH_PORT eth_port_num,				 unsigned char *p_addr,				 ETH_QUEUE queue,				 int option);#endif/* PHY and MIB routines */static bool ethernet_phy_reset(ETH_PORT eth_port_num);static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,				   unsigned int phy_reg,				   unsigned int value);static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,				  unsigned int phy_reg,				  unsigned int* value);static void eth_clear_mib_counters(ETH_PORT	eth_port_num);/* Port data flow control routines */static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,					     ETH_QUEUE tx_queue,					     PKT_INFO *p_pkt_info);static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,					      ETH_QUEUE tx_queue,					      PKT_INFO *p_pkt_info);static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,					     ETH_QUEUE rx_queue,					     PKT_INFO *p_pkt_info);static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,					      ETH_QUEUE rx_queue,					      PKT_INFO *p_pkt_info);static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,				    ETH_QUEUE	tx_queue,				    int				tx_desc_num,				    int				tx_buff_size,				    unsigned int	tx_desc_base_addr,				    unsigned int	tx_buff_base_addr);static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,				    ETH_QUEUE	rx_queue,				    int				rx_desc_num,				    int				rx_buff_size,				    unsigned int	rx_desc_base_addr,				    unsigned int	rx_buff_base_addr);#endif /* MV64360_ETH_ */