/* * (C) Copyright 2005 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <common.h>#include <asm/processor.h>#include <command.h>#include <malloc.h>extern void lxt971_no_sleep(void);/* fpga configuration data - not compressed, generated by bin2c */const unsigned char fpgadata[] ={#include "fpgadata.c"};int filesize = sizeof(fpgadata);int board_early_init_f (void){	/*	 * IRQ 0-15  405GP internally generated; active high; level sensitive	 * IRQ 16    405GP internally generated; active low; level sensitive	 * IRQ 17-24 RESERVED	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive	 */	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */	mtdcr(uicer, 0x00000000);       /* disable all ints */	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */	mtdcr(uictr, 0x10000000);       /* set int trigger levels */	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */	/*	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us	 */	mtebc (epcr, 0xa8400000); /* ebc always driven */	/*	 * Reset CPLD via GPIO12 (CS3) pin	 */	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);	udelay(1000); /* wait 1ms */	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);	udelay(1000); /* wait 1ms */	return 0;}/* ------------------------------------------------------------------------- */int misc_init_f (void){	return 0;  /* dummy implementation */}int misc_init_r (void){	DECLARE_GLOBAL_DATA_PTR;	/* adjust flash start and offset */	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;	gd->bd->bi_flashoffset = 0; 	/*	 * Setup and enable EEPROM write protection	 */	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);	/*	 * Set NAND-FLASH GPIO signals to default	 */	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);	return (0);}/* * Check Board Identity: */int checkboard (void){	unsigned char str[64];	int flashcnt;	int delay;	volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);	volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);	puts ("Board: ");	if (getenv_r("serial#", str, sizeof(str))  == -1) {		puts ("### No HW ID - assuming CMS700");	} else {		puts(str);	}	printf(" (PLD-Version=%02d)\n", *ver_reg);	/*	 * Flash LEDs	 */	for (flashcnt = 0; flashcnt < 3; flashcnt++) {		*led_reg = 0x00;        /* LEDs off */		for (delay = 0; delay < 100; delay++)			udelay(1000);		*led_reg = 0x0f;        /* LEDs on */		for (delay = 0; delay < 50; delay++)			udelay(1000);	}	*led_reg = 0x70;	return 0;}/* ------------------------------------------------------------------------- */long int initdram (int board_type){	unsigned long val;	mtdcr(memcfga, mem_mb0cf);	val = mfdcr(memcfgd);#if 0	printf("\nmb0cf=%x\n", val); /* test-only */	printf("strap=%x\n", mfdcr(strap)); /* test-only */#endif	return (4*1024*1024 << ((val & 0x000e0000) >> 17));}/* ------------------------------------------------------------------------- */#if defined(CFG_EEPROM_WREN)/* Input: <dev_addr>  I2C address of EEPROM device to enable. *         <state>     -1: deliver current state *	               0: disable write *		       1: enable write *  Returns:           -1: wrong device address *                      0: dis-/en- able done *		     0/1: current state if <state> was -1. */int eeprom_write_enable (unsigned dev_addr, int state){	if (CFG_I2C_EEPROM_ADDR != dev_addr) {		return -1;	} else {		switch (state) {		case 1:			/* Enable write access, clear bit GPIO_SINT2. */			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);			state = 0;			break;		case 0:			/* Disable write access, set bit GPIO_SINT2. */			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);			state = 0;			break;		default:			/* Read current status back. */			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));			break;		}	}	return state;}int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){	int query = argc == 1;	int state = 0;	if (query) {		/* Query write access state. */		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);		if (state < 0) {			puts ("Query of write access state failed.\n");		} else {			printf ("Write access for device 0x%0x is %sabled.\n",				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");			state = 0;		}	} else {		if ('0' == argv[1][0]) {			/* Disable write access. */			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);		} else {			/* Enable write access. */			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);		}		if (state < 0) {			puts ("Setup of write access state failed.\n");		}	}	return state;}U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,	   "eepwren - Enable / disable / query EEPROM write access\n",	   NULL);#endif /* #if defined(CFG_EEPROM_WREN) *//* ------------------------------------------------------------------------- */#if (CONFIG_COMMANDS & CFG_CMD_NAND)#include <linux/mtd/nand.h>extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];void nand_init(void){	nand_probe(CFG_NAND_BASE);	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {		print_size(nand_dev_desc[0].totlen, "\n");	}}#endifvoid reset_phy(void){#ifdef CONFIG_LXT971_NO_SLEEP	/*	 * Disable sleep mode in LXT971	 */	lxt971_no_sleep();#endif}