?? controllogic.vhd
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--****************************************************************************************************
-- Control logic for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 11.02.2003
-- Version 0.2A
-- LDM/STM state machines have been significantly changed (not tested yet)
--****************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.ARMPackage.all;
entity ControlLogic is port(
-- Clock and reset
nRESET : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Control signals commom for several modules
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
BigEndianMode : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Instruction pipeline and data in registers control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Interfaces for the internal CPU modules
InstForDecode : in std_logic_vector(31 downto 0);
InstFetchAbort : in std_logic;
StagnatePipeline : out std_logic;
StagnatePipelineDel : out std_logic;
FirstInstFetch : out std_logic;
-- Data out register and control(sign/zero, byte/halfword extension)
SignExt : out std_logic;
ZeroExt : out std_logic;
nB_HW : out std_logic;
-- Bus control
EndianMode : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Data output register control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
StoreHalfWord : out std_logic;
StoreByte : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Address multiplexer and incrementer control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ExceptionVector : out std_logic_vector(31 downto 0);
PCInSel : out std_logic;
ALUInSel : out std_logic;
ExceptionVectorSel : out std_logic;
PCIncStep : out std_logic; -- ?? Common 1
AdrIncStep : out std_logic;
AdrToPCSel : out std_logic;
AdrCntEn : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- ALU control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
InvA : out std_logic;
InvB : out std_logic;
PassA : out std_logic;
PassB : out std_logic; -- MOV/MVN operations
-- Logic operations
AND_Op : out std_logic;
ORR_Op : out std_logic;
EOR_Op : out std_logic;
CFlagUse : out std_logic; -- ADC/SBC/RSC instructions
-- Flag outputs
CFlagOut : in std_logic;
VFlagOut : in std_logic;
NFlagOut : in std_logic;
ZFlagOut : in std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Multiplier control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
LoadRsRm : out std_logic; -- Load Rs and Rm and start
LoadPS : out std_logic; -- Load partial sum register with RHi:RLo
ClearPSC : out std_logic; -- Clear prtial sum register
UnsignedMul : out std_logic; -- Unsigned multiplication
ReadLH : out std_logic; -- 0 - Read PS/PC low,1 - Read PS/PC high
MulResRdy : in std_logic; -- Multiplication result is ready
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Register file control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ABusRdAdr : out std_logic_vector(3 downto 0);
BBusRdAdr : out std_logic_vector(3 downto 0);
WriteAdr : out std_logic_vector(3 downto 0);
WrEn : out std_logic;
-- Program counter
PCWrEn : out std_logic;
PCSrcSel : out std_logic;
-- Mode control signals
RFMode : out std_logic_vector(4 downto 0);
SaveBaseReg : out std_logic;
RestoreBaseReg : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Programm Status Registers control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- ALU bus input control
PSRDInSel : out std_logic;
-- Current program state
CPSRIn : out std_logic_vector(31 downto 0);
CPSRWrEn : out std_logic_vector(31 downto 0);
CPSROut : in std_logic_vector(31 downto 0);
CFlForMul : out std_logic;
-- Saved program state
SPSRIn : out std_logic_vector(31 downto 0);
SPSROut : in std_logic_vector(31 downto 0);
SPSRWrMsk : out std_logic_vector(3 downto 0);
-- PSR mode control
PSRMode : out std_logic_vector(4 downto 0);
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Shifter control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- ShCFlagIn : out std_logic; -- Input of the carry flag
-- ShCFlagOut : in std_logic; -- Output of the carry flag
ShLenImm : out std_logic_vector(4 downto 0); -- Shift amount for immediate shift (bits [11..7])
ShType : out std_logic_vector(2 downto 0); -- Shift type (bits 6,5 and 4 of instruction)
ShRotImm : out std_logic; -- Rotate immediate 8-bit value
ShEn : out std_logic;
ShCFlagEn : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Bus A multiplexer control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
RegFileAOutSel : out std_logic;
MultiplierAOutSel : out std_logic;
CPSROutSel : out std_logic;
SPSROutSel : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Bus B multiplexer control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
RegFileBOutSel : out std_logic; -- Output of the register file
MultiplierBOutSel : out std_logic; -- Output of the multiplier
MemDataRegOutSel : out std_logic; -- Output of the data in register
SExtOffset24BitSel : out std_logic;
Offset12BitSel : out std_logic;
Offset8BitSel : out std_logic;
Immediate8BitSel : out std_logic;
AdrGenDataSel : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Address generator for Load/Store instructions control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
RegisterList : out std_logic_vector(15 downto 0);
IncBeforeSel : out std_logic;
DecBeforeSel : out std_logic;
DecAfterSel : out std_logic;
MltAdrSel : out std_logic;
SngMltSel : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Bit 0,1 clear/set control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ClrBitZero : out std_logic;
ClrBitOne : out std_logic;
SetBitZero : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Thumb decoder control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ThumbDecoderEn : out std_logic;
ThBLFP : in std_logic;
ThBLSP : in std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Rm[0] input for ARM/Thumb state detection during BX
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
RmBitZero : in std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- External signals
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Interrupts
nIRQ : in std_logic;
nFIQ : in std_logic;
-- Bus control
CFGBIGEND : in std_logic;
-- Arbitration
DMORE : out std_logic;
LOCK : out std_logic;
-- Memory interface
ABORT : in std_logic;
WRITE : out std_logic;
SIZE : out std_logic_vector(1 downto 0);
PROT : out std_logic_vector(1 downto 0);
TRANS : out std_logic_vector(1 downto 0);
-- Memory management interface
CPnTRANS : out std_logic;
CPnOPC : out std_logic;
-- Coprocessor interface
CPnMREQ : out std_logic;
CPnSEQ : out std_logic;
CPTBIT : out std_logic;
CPnI : out std_logic;
CPA : in std_logic;
CPB : in std_logic
);
end ControlLogic;
architecture RTL of ControlLogic is
-- Saved value of InstForDecode input(valid for the whole time of instruction execution)
signal InstForDecodeLatched : std_logic_vector(InstForDecode'range) := (others =>'0');
-- Saved abort flag
signal IFAbtStored : std_logic := '0';
alias opcode : std_logic_vector(3 downto 0) is InstForDecode(24 downto 21);
alias shift_amount : std_logic_vector(4 downto 0) is InstForDecode(11 downto 7);
alias shift : std_logic_vector(1 downto 0) is InstForDecode(6 downto 5);
alias rotate : std_logic_vector(3 downto 0) is InstForDecode(11 downto 8);
alias register_list : std_logic_vector(15 downto 0) is InstForDecode(15 downto 0);
--alias offset24b : std_logic_vector(23 downto 0) is InstForDecode(23 downto 0);
alias swi_number : std_logic_vector(23 downto 0) is InstForDecode(23 downto 0);
alias cond : std_logic_vector(3 downto 0) is InstForDecodeLatched(31 downto 28);
alias Mask : std_logic_vector(3 downto 0) is InstForDecodeLatched(19 downto 16);
-- Load/store fields !!! TBD
alias U : std_logic is InstForDecode(23);
alias P : std_logic is InstForDecode(24);
alias W : std_logic is InstForDecode(21);
-- Latched load/store fields
alias U_Latched : std_logic is InstForDecodeLatched(23);
alias P_Latched : std_logic is InstForDecodeLatched(24);
alias W_Latched : std_logic is InstForDecodeLatched(21);
alias S_Latched : std_logic is InstForDecodeLatched(20);
alias R_Latched : std_logic is InstForDecodeLatched(22);
alias L_Latched : std_logic is InstForDecodeLatched(20); -- '1' - Load / '0' - Store
-- Rgisters
alias Rn : std_logic_vector(3 downto 0) is InstForDecodeLatched(19 downto 16);
alias Rd : std_logic_vector(3 downto 0) is InstForDecodeLatched(15 downto 12);
alias Rs : std_logic_vector(3 downto 0) is InstForDecodeLatched(11 downto 8);
alias Rm : std_logic_vector(3 downto 0) is InstForDecodeLatched(3 downto 0);
-- Multiplication
alias RdM : std_logic_vector(3 downto 0) is InstForDecodeLatched(19 downto 16);
alias RnM : std_logic_vector(3 downto 0) is InstForDecodeLatched(15 downto 12);
alias RdHi : std_logic_vector(3 downto 0) is InstForDecodeLatched(19 downto 16);
alias RdLo : std_logic_vector(3 downto 0) is InstForDecodeLatched(15 downto 12);
constant SBO : std_logic_vector(3 downto 0) := (others => '1');
constant SBZ : std_logic_vector(3 downto 0) := (others => '0');
signal WriteToPC : std_logic := '0'; -- Write to R15
signal WriteToHiFl : std_logic := '0'; -- Data processing instruction writes to N,Z,C,V flags of CPSR
signal RestCPSR : std_logic := '0'; -- Restore CPSR from the appropriate SPSR
signal WriteToCPSR : std_logic := '0'; -- Write to CPSR
signal MulFlWr : std_logic := '0'; -- Write to Z and C flag by multiplications
-- Instructions
-- Data processing instructions
signal IDC_AND : std_logic := '0';
signal IDC_EOR : std_logic := '0';
signal IDC_ORR : std_logic := '0';
signal IDC_BIC : std_logic := '0';
signal IDC_TST : std_logic := '0';
signal IDC_TEQ : std_logic := '0';
signal IDC_ADD : std_logic := '0';
signal IDC_ADC : std_logic := '0';
signal IDC_SUB : std_logic := '0';
signal IDC_SBC : std_logic := '0';
signal IDC_RSB : std_logic := '0';
signal IDC_RSC : std_logic := '0';
signal IDC_CMP : std_logic := '0';
signal IDC_CMN : std_logic := '0';
signal IDC_MOV : std_logic := '0';
signal IDC_MVN : std_logic := '0';
-- Multiplications
signal IDC_MUL : std_logic := '0';
signal IDC_MLA : std_logic := '0';
signal IDC_UMULL : std_logic := '0';
signal IDC_UMLAL : std_logic := '0';
signal IDC_SMULL : std_logic := '0';
signal IDC_SMLAL : std_logic := '0';
--SPSR Move
signal IDC_MSR_R : std_logic := '0'; -- Register operand
signal IDC_MSR_I : std_logic := '0'; -- Immediate operand
signal IDC_MRS : std_logic := '0';
-- Branch
signal IDC_B : std_logic := '0';
signal IDC_BL : std_logic := '0';
signal IDC_BX : std_logic := '0';
-- Load
signal IDC_LDR : std_logic := '0';
signal IDC_LDRT : std_logic := '0';
signal IDC_LDRB : std_logic := '0';
signal IDC_LDRBT : std_logic := '0';
signal IDC_LDRSB : std_logic := '0';
signal IDC_LDRH : std_logic := '0';
signal IDC_LDRSH : std_logic := '0';
signal IDC_LDM : std_logic := '0'; -- ?? Variants
-- Store
signal IDC_STR : std_logic := '0';
signal IDC_STRT : std_logic := '0';
signal IDC_STRB : std_logic := '0';
signal IDC_STRBT : std_logic := '0';
signal IDC_STRH : std_logic := '0';
signal IDC_STM : std_logic := '0'; -- ?? Variants
-- Swap
signal IDC_SWP : std_logic := '0';
signal IDC_SWPB : std_logic := '0';
signal IDC_SWI : std_logic := '0';
-- Coprocessor communication instructions
signal IDC_MRC : std_logic := '0';
signal IDC_MCR : std_logic := '0';
signal IDC_LDC : std_logic := '0';
signal IDC_CDP : std_logic := '0';
signal IDC_STC : std_logic := '0';
-- Undefined instruction
signal IDC_Undef : std_logic := '0';
-- End of instruction decoder signals
-- Registeres instruction decoder outputs
-- Data processing instructions
signal IDR_AND : std_logic := '0';
signal IDR_EOR : std_logic := '0';
signal IDR_ORR : std_logic := '0';
signal IDR_BIC : std_logic := '0';
signal IDR_TST : std_logic := '0';
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