?? controllogic.vhd
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IDC_RSC <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="0111" and
IDC_ArInstExtSp='0' else '0';
-- Move
IDC_MOV <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="1101" and
IDC_ArInstExtSp='0' else '0';
IDC_MVN <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="1111" and
IDC_ArInstExtSp='0' else '0';
-- Instructions which only can change CPSR flags (compare)
IDC_CMP <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 20)="10101" and
IDC_ArInstExtSp='0' else '0';
IDC_CMN <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 20)="10111" and
IDC_ArInstExtSp='0' else '0';
IDC_TST <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 20)="10001" and
IDC_ArInstExtSp='0' else '0';
IDC_TEQ <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 20)="10011" and
IDC_ArInstExtSp='0' else '0';
-- End of data processing instructions
-- Multiplications
IDC_MUL <= '1' when InstForDecode(27 downto 21)="0000000" and
InstForDecode(7 downto 4)="1001" else '0';
IDC_MLA <= '1' when InstForDecode(27 downto 21)="0000001" and
InstForDecode(7 downto 4)="1001" else '0';
IDC_UMULL <= '1' when InstForDecode(27 downto 21)="0000100" and
InstForDecode(7 downto 4)="1001" else '0';
IDC_UMLAL <= '1' when InstForDecode(27 downto 21)="0000101" and
InstForDecode(7 downto 4)="1001" else '0';
IDC_SMULL <= '1' when InstForDecode(27 downto 21)="0000110" and
InstForDecode(7 downto 4)="1001" else '0';
IDC_SMLAL <= '1' when InstForDecode(27 downto 21)="0000111" and
InstForDecode(7 downto 4)="1001" else '0';
-- Move immediate value to status register(CPSR/SPSR)
-- (works like data processing instruction with immediate)
IDC_MSR_I <= '1' when InstForDecode(27 downto 23)="00110" and
InstForDecode(21 downto 20)="10" else '0';
-- Move register value to status register(CPSR/SPSR)
-- (works like data processing instruction with immediate)
IDC_MSR_R <= '1' when InstForDecode(27 downto 23)="00010" and
InstForDecode(21 downto 20)="10" and
InstForDecode(7 downto 4)="0000" else '0';
-- Move status register(CPSR/SPSR) to general purpose register
IDC_MRS <= '1' when InstForDecode(27 downto 23)="00010" and
InstForDecode(21 downto 20)="00" and
InstForDecode(7 downto 4)="0000" else '0';
-- Branch
IDC_B <= '1' when InstForDecode(27 downto 24)="1010" else '0'; -- ?? Merge
IDC_BL <= '1' when InstForDecode(27 downto 24)="1011" else '0'; -- ?? Merge
IDC_BX <= '1' when InstForDecode(27 downto 20)="00010010" and
InstForDecode(7 downto 4)="0001" else '0';
-- Load
IDC_LDR <= '1' when InstForDecode(27 downto 26)="01" and
InstForDecode(22)='0' and InstForDecode(20)='1' else '0';
-- Load byte !!! TBD
IDC_LDRB <= '1' when InstForDecode(27 downto 26)="01" and
InstForDecode(22)='1' and InstForDecode(20)='1' else '0';
-- Load byte with translation !!! TBD
IDC_LDRBT <= '1' when InstForDecode(27 downto 26)="01" and
InstForDecode(24)='0' and
InstForDecode(22 downto 20)="111" else '0';
-- Load halfword !!! TBD
IDC_LDRH <= '1' when InstForDecode(27 downto 25)="000" and
InstForDecode(20)='1' and
InstForDecode(7 downto 4)="1011" else '0';
-- Load signed byte !!! TBD
IDC_LDRSB <= '1' when InstForDecode(27 downto 25)="000" and
InstForDecode(20)='1' and
InstForDecode(7 downto 4)="1101" else '0';
-- Load signed halfword !!! TBD
IDC_LDRSH <= '1' when InstForDecode(27 downto 25)="000" and
InstForDecode(20)='1' and
InstForDecode(7 downto 4)="1111" else '0';
-- Load word with translation !!! TBD
IDC_LDRT <= '1' when InstForDecode(27 downto 26)="01" and
InstForDecode(24)='0' and
InstForDecode(22 downto 20)="011" else '0';
-- All the types of load multiple registers
IDC_LDM <= '1' when InstForDecode(27 downto 25)="100" and
InstForDecode(20)='1' else '0';
-- Store
IDC_STR <= '1' when InstForDecode(27 downto 26)="01" and
InstForDecode(22)='0' and InstForDecode(20)='0' else '0';
-- Store byte !!! TBD
IDC_STRB <= '1' when InstForDecode(27 downto 26)="01" and
InstForDecode(22)='1' and InstForDecode(20)='0' else '0';
-- Store byte with translation !!! TBD
IDC_STRBT <= '1' when InstForDecode(27 downto 26)="01" and
InstForDecode(24)='0' and
InstForDecode(22 downto 20)="110" else '0';
-- Store halfword !!! TBD
IDC_STRH <= '1' when InstForDecode(27 downto 25)="000" and
InstForDecode(20)='0' and
InstForDecode(7 downto 4)="1011" else '0';
-- Store word with translation !!! TBD
IDC_STRT <= '1' when InstForDecode(27 downto 26)="01" and
InstForDecode(24)='0' and
InstForDecode(22 downto 20)="010" else '0';
-- All the types of store multiple registers
IDC_STM <= '1' when InstForDecode(27 downto 25)="100" and
InstForDecode(20)='0' else '0';
-- Swap word
IDC_SWP <= '1' when InstForDecode(27 downto 20)="00010000" and
InstForDecode(7 downto 4)="1001" else '0';
-- Swap byte
IDC_SWPB <= '1' when InstForDecode(27 downto 20)="00010100" and
InstForDecode(7 downto 4)="1001" else '0';
-- Software interrupt
IDC_SWI <= '1' when InstForDecode(27 downto 24)="1111" else '0';
-- Coprocessor instructions
IDC_MRC <= '1' when InstForDecode(27 downto 24)="1110" and
InstForDecode(20)='1' and InstForDecode(4)='1' else '0';
IDC_MCR <= '1' when InstForDecode(27 downto 24)="1110" and
InstForDecode(20)='0' and InstForDecode(4)='1' else '0';
IDC_LDC <= '1' when InstForDecode(27 downto 25)="110" and
InstForDecode(20)='1' else '0';
IDC_CDP <= '1' when InstForDecode(27 downto 24)="1110" and
InstForDecode(4)='0' else '0';
IDC_STC <= '1' when InstForDecode(27 downto 25)="110" and
InstForDecode(20)='0' else '0';
IDC_Undef <= '1' when InstForDecode(27 downto 25)="011" and -- TBD
InstForDecode(4)='1' else '0';
-- Instruction groops
-- Data processing immediate shift (shift)
IDC_DPIImmSh <= '1' when InstForDecode(27 downto 25)="000" and InstForDecode(4)='0' and
not(InstForDecode(24 downto 23)="10" and InstForDecode(20)='0') else '0';
-- Data processing register shift
IDC_DPIRegSh <= '1' when InstForDecode(27 downto 25)="000" and InstForDecode(7)='0' and InstForDecode(4)='1' and
not((InstForDecode(24 downto 23)="10" and InstForDecode(20)='0')or
(InstForDecode(7)='1' and InstForDecode(4)='1')) else '0';
-- Data processing immediate (rotate)
IDC_DPIImmRot <= '1' when InstForDecode(27 downto 25)="001" and
not(InstForDecode(24 downto 23)="10" and InstForDecode(20)='0')
else '0';
-- Load/store register offset(shift)
IDC_LSRegOffset <= '1' when InstForDecode(27 downto 25)="011" and
InstForDecode(4)='0' else '0';
-- Load/store immediate offset
IDC_LSImmOffset <= '1' when InstForDecode(27 downto 25)="010" else '0';
-- Load/store(halfword) register offset
IDC_LSHWRegOffset <= '1' when InstForDecode(27 downto 25)="000" and
InstForDecode(22)='0' and InstForDecode(7 downto 4)="1011"
else '0';
-- Load/store(halfword) immediate offset
IDC_LSHWImmOffset <= '1' when InstForDecode(27 downto 25)="000" and
InstForDecode(22)='1' and InstForDecode(7 downto 4)="1011"
else '0';
-- Load signed (halfword/byte) register offset
IDC_LHWBSRegOffset <= '1' when InstForDecode(27 downto 25)="000" and
InstForDecode(22)='0' and
InstForDecode(20)='1' and
InstForDecode(7 downto 6)="11" and
InstForDecode(4)='1'
else '0';
-- Load signed (halfword/byte) immediate offset
IDC_LHWBSImmOffset <= '1' when InstForDecode(27 downto 25)="000" and
InstForDecode(22)='1' and
InstForDecode(20)='1' and
InstForDecode(7 downto 6)="11" and
InstForDecode(4)='1'
else '0';
-- All of the load/store(multiple)
IDC_LdStInst <= IDC_LDR or IDC_LDRT or IDC_LDRB or IDC_LDRBT or IDC_LDRSB or
IDC_LDRH or IDC_LDRSH or IDC_LDM or IDC_STR or IDC_STRT or
IDC_STRB or IDC_STRBT or IDC_STRH or IDC_STM;
IDC_Branch <= IDC_B or IDC_BL or IDC_BX;
IDC_Compare <= IDC_TST or IDC_TEQ or IDC_CMP or IDC_CMN;
IDC_DPIArith <= IDC_ADD or IDC_ADC or IDC_SUB or IDC_SBC or
IDC_RSB or IDC_RSC or IDC_CMP or IDC_CMN;
-- *******************************************************************************************
-- End of the instruction decoder
-- *******************************************************************************************
-- Instruction decoder register
InstrDecoderRegs:process(nRESET,CLK)
begin
if nRESET='0' then -- Reset
IDR_AND <= '0';
IDR_EOR <= '0';
IDR_ORR <= '0';
IDR_BIC <= '0';
IDR_TST <= '0';
IDR_TEQ <= '0';
IDR_ADD <= '0';
IDR_ADC <= '0';
IDR_SUB <= '0';
IDR_SBC <= '0';
IDR_RSB <= '0';
IDR_RSC <= '0';
IDR_CMP <= '0';
IDR_CMN <= '0';
IDR_MOV <= '0';
IDR_MVN <= '0';
IDR_MUL <= '0';
IDR_MLA <= '0';
IDR_UMULL <= '0';
IDR_UMLAL <= '0';
IDR_SMULL <= '0';
IDR_SMLAL <= '0';
IDR_MSR_R <= '0';
IDR_MSR_I <= '0';
IDR_MRS <= '0';
IDR_B <= '0';
IDR_BL <= '0';
IDR_BX <= '0';
IDR_LDR <= '0';
IDR_LDRT <= '0';
IDR_LDRB <= '0';
IDR_LDRBT <= '0';
IDR_LDRSB <= '0';
IDR_LDRH <= '0';
IDR_LDRSH <= '0';
IDR_LDM <= '0';
IDR_STR <= '0';
IDR_STRT <= '0';
IDR_STRB <= '0';
IDR_STRBT <= '0';
IDR_STRH <= '0';
IDR_STM <= '0';
IDR_SWP <= '0';
IDR_SWPB <= '0';
IDR_SWI <= '0';
IDR_MRC <= '0';
IDR_MCR <= '0';
IDR_LDC <= '0';
IDR_CDP <= '0';
IDR_STC <= '0';
-- Thumb branch with link support
IDR_ThBLFP <= '0';
IDR_ThBLSP <= '0';
IDR_Undef <= '0';
-- Instruction groops
IDR_DPIRegSh <= '0';
IDR_DPIImmSh <= '0';
IDR_DPIImmRot <= '0';
IDR_LSRegOffset <= '0';
IDR_LSImmOffset <= '0';
IDR_LSHWImmOffset <= '0';
IDR_LSHWRegOffset <= '0';
IDR_LHWBSImmOffset <= '0';
IDR_LHWBSRegOffset <= '0';
IDR_LdStInst <= '0';
IDR_SingleCycleDPI <= '0';
IDR_Branch <= '0';
IDR_Compare <= '0';
IDR_DPIArith <= '0';
-- Stored instruction and it's abort indicator
InstForDecodeLatched <= ( others => '0');
IFAbtStored <= '0';
-- External interrupt requests syncronization with instruction execution
FIQLatched <= '0';
IRQLatched <= '0';
elsif CLK='1' and CLK'event then -- Clock
if StagnatePipeline_Int='0' and CLKEN='1' then -- Clock enable
IDR_AND <= IDC_AND;
IDR_EOR <= IDC_EOR;
IDR_ORR <= IDC_ORR;
IDR_BIC <= IDC_BIC;
IDR_TST <= IDC_TST;
IDR_TEQ <= IDC_TEQ;
IDR_ADD <= IDC_ADD;
IDR_ADC <= IDC_ADC;
IDR_SUB <= IDC_SUB;
IDR_SBC <= IDC_SBC;
IDR_RSB <= IDC_RSB;
IDR_RSC <= IDC_RSC;
IDR_CMP <= IDC_CMP;
IDR_CMN <= IDC_CMN;
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