?? arm7tdmis_top.vhd
字號:
CLK : in std_logic;
CLKEN : in std_logic;
-- Control and data
RmDataIn : in std_logic_vector(31 downto 0);
BDataOut : out std_logic_vector(31 downto 0);
RegisterList : in std_logic_vector(15 downto 0);
IncBeforeSel : in std_logic;
DecBeforeSel : in std_logic;
DecAfterSel : in std_logic;
MltAdrSel : in std_logic; -- 0 -> Start address, 1-> Base reg. update (only for LDM/STM)
SngMltSel : in std_logic -- 0 -> LDM/STM, 1 -> LDR/STR
);
end component;
component ResltBitMask is port(
-- Data
DataIn : in std_logic_vector(31 downto 0);
DataOut : out std_logic_vector(31 downto 0);
-- Control
ClrBitZero : in std_logic;
ClrBitOne : in std_logic;
SetBitZero : in std_logic
);
end component;
-- Combinatorial Thumb decoder
component ThumbDecoder is port(
InstForDecode : in std_logic_vector(31 downto 0);
ExpandedInst : out std_logic_vector(31 downto 0);
HalfWordAddress : in std_logic;
ThumbDecoderEn : in std_logic;
ThBLFP : out std_logic;
ThBLSP : out std_logic
);
end component;
-- Control logic
component ControlLogic is port(
-- Clock and reset
nRESET : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Control signals commom for several modules
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
BigEndianMode : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Instruction pipeline and data in registers control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Interfaces for the internal CPU modules
InstForDecode : in std_logic_vector(31 downto 0);
InstFetchAbort : in std_logic;
StagnatePipeline : out std_logic;
StagnatePipelineDel : out std_logic;
FirstInstFetch : out std_logic;
-- Data out register and control(sign/zero, byte/halfword extension)
SignExt : out std_logic;
ZeroExt : out std_logic;
nB_HW : out std_logic;
-- Bus control
EndianMode : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Data output register control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
StoreHalfWord : out std_logic;
StoreByte : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Address multiplexer and incrementer control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ExceptionVector : out std_logic_vector(31 downto 0);
PCInSel : out std_logic;
ALUInSel : out std_logic;
ExceptionVectorSel : out std_logic;
PCIncStep : out std_logic; -- ?? Common 1
AdrIncStep : out std_logic;
AdrToPCSel : out std_logic;
AdrCntEn : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- ALU control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
InvA : out std_logic;
InvB : out std_logic;
PassA : out std_logic;
PassB : out std_logic; -- MOV/MVN operations
-- Logic operations
AND_Op : out std_logic;
ORR_Op : out std_logic;
EOR_Op : out std_logic;
-- Flag inputs
CFlagUse : out std_logic; -- ADC/SBC/RSC instructions
-- Flag outputs
CFlagOut : in std_logic;
VFlagOut : in std_logic;
NFlagOut : in std_logic;
ZFlagOut : in std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Multiplier control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
LoadRsRm : out std_logic; -- Load Rs and Rm and start
LoadPS : out std_logic; -- Load partial sum register with RHi:RLo
ClearPSC : out std_logic; -- Clear prtial sum register
UnsignedMul : out std_logic; -- Unsigned multiplication
ReadLH : out std_logic; -- 0 - Read PS/PC low,1 - Read PS/PC high
MulResRdy : in std_logic; -- Multiplication result is ready
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Register file control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ABusRdAdr : out std_logic_vector(3 downto 0);
BBusRdAdr : out std_logic_vector(3 downto 0);
WriteAdr : out std_logic_vector(3 downto 0);
WrEn : out std_logic;
-- Program counter
PCWrEn : out std_logic;
PCSrcSel : out std_logic;
-- Mode control signals
RFMode : out std_logic_vector(4 downto 0);
SaveBaseReg : out std_logic;
RestoreBaseReg : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Programm Status Registers control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- ALU bus input control
PSRDInSel : out std_logic;
-- Current program state
CPSRIn : out std_logic_vector(31 downto 0);
CPSRWrEn : out std_logic_vector(31 downto 0);
CPSROut : in std_logic_vector(31 downto 0);
CFlForMul : out std_logic;
-- Saved program state
SPSRIn : out std_logic_vector(31 downto 0);
SPSROut : in std_logic_vector(31 downto 0);
SPSRWrMsk : out std_logic_vector(3 downto 0);
-- PSR mode control
PSRMode : out std_logic_vector(4 downto 0);
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Shifter control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- ShCFlagIn : out std_logic; -- Input of the carry flag
-- ShCFlagOut : in std_logic; -- Output of the carry flag
ShLenImm : out std_logic_vector(4 downto 0); -- Shift amount for immediate shift (bits [11..7])
ShType : out std_logic_vector(2 downto 0); -- Shift type (bits 6,5 and 4 of instruction)
ShRotImm : out std_logic; -- Rotate immediate 8-bit value
ShEn : out std_logic;
ShCFlagEn : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Bus A multiplexer control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
RegFileAOutSel : out std_logic;
MultiplierAOutSel : out std_logic;
CPSROutSel : out std_logic;
SPSROutSel : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Bus B multiplexer control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
RegFileBOutSel : out std_logic; -- Output of the register file
MultiplierBOutSel : out std_logic; -- Output of the multiplier
MemDataRegOutSel : out std_logic; -- Output of the data in register
SExtOffset24BitSel : out std_logic;
Offset12BitSel : out std_logic;
Offset8BitSel : out std_logic;
Immediate8BitSel : out std_logic;
AdrGenDataSel : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Address generator for Load/Store instructions control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
RegisterList : out std_logic_vector(15 downto 0);
IncBeforeSel : out std_logic;
DecBeforeSel : out std_logic;
DecAfterSel : out std_logic;
MltAdrSel : out std_logic;
SngMltSel : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Bit 0,1 clear/set control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ClrBitZero : out std_logic;
ClrBitOne : out std_logic;
SetBitZero : out std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Thumb decoder control
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ThumbDecoderEn : out std_logic;
ThBLFP : in std_logic;
ThBLSP : in std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Rm[0] input for ARM/Thumb state detection during BX
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
RmBitZero : in std_logic;
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- External signals
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Interrupts
nIRQ : in std_logic;
nFIQ : in std_logic;
-- Bus control
CFGBIGEND : in std_logic;
-- Arbitration
DMORE : out std_logic;
LOCK : out std_logic;
-- Memory interface
ABORT : in std_logic;
WRITE : out std_logic;
SIZE : out std_logic_vector(1 downto 0);
PROT : out std_logic_vector(1 downto 0);
TRANS : out std_logic_vector(1 downto 0);
-- Memory management interface
CPnTRANS : out std_logic;
CPnOPC : out std_logic;
-- Coprocessor interface
CPnMREQ : out std_logic;
CPnSEQ : out std_logic;
CPTBIT : out std_logic;
CPnI : out std_logic;
CPA : in std_logic;
CPB : in std_logic
);
end component;
-- ALU signals
signal ALU_DataOut : std_logic_vector(31 downto 0) := (others => '0');
signal ALU_InvA : std_logic := '0';
signal ALU_InvB : std_logic := '0';
signal ALU_PassA : std_logic := '0';
signal ALU_PassB : std_logic := '0';
signal ALU_AND_Op : std_logic := '0';
signal ALU_ORR_Op : std_logic := '0';
signal ALU_EOR_Op : std_logic := '0';
signal ALU_CFlagIn : std_logic := '0';
signal ALU_CFlagUse : std_logic := '0';
signal ALU_CFlagOut : std_logic := '0';
signal ALU_VFlagOut : std_logic := '0';
signal ALU_NFlagOut : std_logic := '0';
signal ALU_ZFlagOut : std_logic := '0';
-- Shifter signals
signal Shifter_ShBBusIn : std_logic_vector(31 downto 0) := (others => '0');
signal Shifter_ShOut : std_logic_vector(31 downto 0) := (others => '0');
signal Shifter_ShCFlagIn : std_logic := '0';
signal Shifter_ShCFlagOut : std_logic := '0';
signal Shifter_ShLenRs : std_logic_vector(7 downto 0) := (others => '0');
signal Shifter_ShLenImm : std_logic_vector(4 downto 0) := (others => '0');
signal Shifter_ShType : std_logic_vector(2 downto 0) := (others => '0');
signal Shifter_ShRotImm : std_logic := '0';
signal Shifter_ShEn : std_logic := '0';
signal Shifter_ShCFlagEn : std_logic := '0';
-- Register file signals
signal RegFile_ABusOut : std_logic_vector(31 downto 0) := (others => '0');
signal RegFile_BBusOut : std_logic_vector(31 downto 0) := (others => '0');
signal RegFile_ABusRdAdr : std_logic_vector(3 downto 0) := (others => '0');
signal RegFile_BBusRdAdr : std_logic_vector(3 downto 0) := (others => '0');
signal RegFile_WriteAdr : std_logic_vector(3 downto 0) := (others => '0');
signal RegFile_WrEn : std_logic := '0';
signal RegFile_PCIn : std_logic_vector(31 downto 0) := (others => '0');
signal RegFile_PCOut : std_logic_vector(31 downto 0) := (others => '0');
signal RegFile_PCWrEn : std_logic := '0';
signal RegFile_PCSrcSel : std_logic := '0';
signal RegFile_RFMode : std_logic_vector(4 downto 0) := (others => '0');
signal RegFile_SaveBaseReg : std_logic := '0';
signal RegFile_RestoreBaseReg : std_logic := '0';
-- Multiplier signals
signal Mult_ADataOut : std_logic_vector(31 downto 0) := (others => '0');
signal Mult_BDataOut : std_logic_vector(31 downto 0) := (others => '0');
signal Mult_LoadRsRm : std_logic := '0';
signal Mult_LoadPS : std_logic := '0';
signal Mult_ClearPSC : std_logic := '0';
signal Mult_UnsignedMul : std_logic := '0';
signal Mult_ReadLH : std_logic := '0';
signal Mult_MulResRdy : std_logic := '0';
-- Program status registers signals
signal PSR_CPSRIn : std_logic_vector(31 downto 0) := (others => '0');
signal PSR_CPSRWrEn : std_logic_vector(31 downto 0) := (others => '0');
signal PSR_CPSROut : std_logic_vector(31 downto 0) := (others => '0');
signal PSR_CFlForMul : std_logic := '0';
signal PSR_SPSRIn : std_logic_vector(31 downto 0) := (others => '0');
signal PSR_SPSRWrMsk : std_logic_vector(3 downto 0) := (others => '0');
signal PSR_SPSROut : std_logic_vector(31 downto 0) := (others => '0');
signal PSR_PSRMode : std_logic_vector(4 downto 0) := (others => '0');
signal PSR_PSRDInSel : std_logic := '0';
alias PSR_CFlagOut : std_logic is PSR_CPSROut(29);
-- Instruction pipeline signals
signal IPDR_InstForDecode : std_logic_vector(31 downto 0) := (others => '0');
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