?? arm7tdmis_top.vhd
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signal IPDR_StagnatePipeline : std_logic := '0';
signal IPDR_StagnatePipelineDel : std_logic := '0';
signal IPRD_FirstInstFetch : std_logic := '0';
signal IPDR_InstFetchAbort : std_logic := '0';
signal IPDR_DataOut : std_logic_vector(31 downto 0) := (others => '0');
signal IPDR_SExtOffset24Bit : std_logic_vector(31 downto 0) := (others => '0');
signal IPDR_Offset12Bit : std_logic_vector(31 downto 0) := (others => '0');
signal IPDR_Offset8Bit : std_logic_vector(31 downto 0) := (others => '0');
signal IPDR_Immediate8Bit : std_logic_vector(31 downto 0) := (others => '0');
signal IPDR_EndianMode : std_logic := '0';
signal IPDR_SignExt : std_logic := '0';
signal IPDR_ZeroExt : std_logic := '0';
signal IPDR_nB_HW : std_logic := '0';
-- Thumb decoder interface
signal IPDR_ToThumbDecoder : std_logic_vector(31 downto 0) := (others => '0');
signal IPDR_FromThumbDecoder : std_logic_vector(31 downto 0) := (others => '0');
signal IPDR_HalfWordAddress : std_logic := '0';
signal ThDC_ThBLFP : std_logic := '0';
signal ThDC_ThBLSP : std_logic := '0';
-- Address multiplexer and incrementer signals
signal AMI_FromPC : std_logic_vector(31 downto 0) := (others => '0');
signal AMI_ToPC : std_logic_vector(31 downto 0) := (others => '0');
signal AMI_FromALU : std_logic_vector(31 downto 0) := (others => '0');
signal AMI_ExceptionVector : std_logic_vector(31 downto 0) := (others => '0');
signal AMI_PCInSel : std_logic := '0';
signal AMI_ALUInSel : std_logic := '0';
signal AMI_ExceptionVectorSel : std_logic := '0';
signal AMI_PCIncStep : std_logic := '0';
signal AMI_AdrIncStep : std_logic := '0';
signal AMI_AdrToPCSel : std_logic := '0';
signal AMI_AdrCntEn : std_logic := '0';
-- Data out register signals
signal DOR_StoreHalfWord : std_logic := '0';
signal DOR_StoreByte : std_logic := '0';
-- Register for shift amount signals
signal RSA_ShLenRsOut : std_logic_vector(7 downto 0) := (others => '0');
-- A bus multiplexer signals
signal ABM_ABusOut : std_logic_vector(31 downto 0) := (others => '0');
signal ABM_RegFileAOutSel : std_logic := '0';
signal ABM_MultiplierAOutSel : std_logic := '0';
signal ABM_CPSROutSel : std_logic := '0';
signal ABM_SPSROutSel : std_logic := '0';
-- B bus multiplexer signals
signal BBM_BBusOut : std_logic_vector(31 downto 0) := (others => '0');
signal BBM_RegFileBOutSel : std_logic := '0';
signal BBM_MultiplierBOutSel : std_logic := '0';
signal BBM_MemDataRegOutSel : std_logic := '0';
signal BBM_SExtOffset24BitSel : std_logic := '0';
signal BBM_Offset12BitSel : std_logic := '0';
signal BBM_Offset8BitSel : std_logic := '0';
signal BBM_Immediate8BitSel : std_logic := '0';
signal BBM_AdrGenDataSel : std_logic := '0';
-- Address generator for load/store signals
signal LSAdrGen_BDataOut : std_logic_vector(31 downto 0) := (others => '0');
signal LSAdrGen_RegisterList : std_logic_vector(15 downto 0) := (others => '0');
signal LSAdrGen_IncBeforeSel : std_logic := '0';
signal LSAdrGen_DecBeforeSel : std_logic := '0';
signal LSAdrGen_DecAfterSel : std_logic := '0';
signal LSAdrGen_MltAdrSel : std_logic := '0';
signal LSAdrGen_SngMltSel : std_logic := '0';
-- Bit 0,1 clearer
signal RBM_DataOut : std_logic_vector(31 downto 0) := (others => '0');
signal RBM_ClrBitZero : std_logic := '0';
signal RBM_ClrBitOne : std_logic := '0';
signal RBM_SetBitZero : std_logic := '0';
-- Thumb decoder signals
signal ThDC_ThumbDecoderEn : std_logic := '0';
-- Internal copies of some core outputs
signal ADDR_Int : std_logic_vector(ADDR'range) := (others => '0');
signal SIZE_Int : std_logic_vector(SIZE'range) := (others => '0');
signal BigEndianMode : std_logic := '0';
begin
ALU_Inst:component ALU port map(
ADataIn => ABM_ABusOut, -- Output of A bus multiplexer
BDataIn => Shifter_ShOut, -- Output of the shifter
DataOut => ALU_DataOut,
InvA => ALU_InvA,
InvB => ALU_InvB,
PassA => ALU_PassA,
PassB => ALU_PassB,
-- Logic operations
AND_Op => ALU_AND_Op,
ORR_Op => ALU_ORR_Op,
EOR_Op => ALU_EOR_Op,
-- Flag inputs
CFlagIn => ALU_CFlagIn,
CFlagUse => ALU_CFlagUse,
-- Flag outputs
CFlagOut => ALU_CFlagOut,
VFlagOut => ALU_VFlagOut,
NFlagOut => ALU_NFlagOut,
ZFlagOut => ALU_ZFlagOut
);
-- Shifter
Shifter_Inst:component Shifter port map(
ShBBusIn => BBM_BBusOut, -- Output of B bus multiplexer
ShOut => Shifter_ShOut, -- To ALU
ShCFlagIn => PSR_CFlagOut,
ShCFlagOut => ALU_CFlagIn, -- To ALU
ShLenRs => Shifter_ShLenRs, -- From shift amount register
ShLenImm => Shifter_ShLenImm, -- From control logic
ShType => Shifter_ShType, -- From control logic
ShRotImm => Shifter_ShRotImm, -- From control logic
ShEn => Shifter_ShEn, -- From control logic
ShCFlagEn => Shifter_ShCFlagEn -- From control logic
);
-- Multiplier
Multiplier_Inst:component Multiplier port map(
-- Global signals
nRESET => nRESET,
CLK => CLK,
CLKEN => CLKEN,
-- Data inputs
ADataIn => RegFile_ABusOut,
BDataIn => RegFile_BBusOut,
-- Data outputs
ADataOut => Mult_ADataOut,
BDataOut => Mult_BDataOut,
-- Control inputs
LoadRsRm => Mult_LoadRsRm,
LoadPS => Mult_LoadPS,
ClearPSC => Mult_ClearPSC,
UnsignedMul => Mult_UnsignedMul,
ReadLH => Mult_ReadLH,
-- Control outputs
MulResRdy => Mult_MulResRdy
);
-- Register file
RegFile_Inst:component RegFile generic map(DebugMode => TRUE)
port map(
-- Global control signals
nRESET => nRESET,
CLK => CLK,
CLKEN => CLKEN,
-- Data buses
ABusOut => RegFile_ABusOut,
BBusOut => RegFile_BBusOut,
DataIn => RBM_DataOut, -- From ALU *
-- Address an control
ABusRdAdr => RegFile_ABusRdAdr,
BBusRdAdr => RegFile_BBusRdAdr,
WriteAdr => RegFile_WriteAdr,
WrEn => RegFile_WrEn,
-- Program counter
PCIn => RegFile_PCIn,
PCOut => RegFile_PCOut,
PCWrEn => RegFile_PCWrEn,
PCSrcSel => RegFile_PCSrcSel,
-- Global control
RFMode => RegFile_RFMode,
SaveBaseReg => RegFile_SaveBaseReg,
RestoreBaseReg => RegFile_RestoreBaseReg
);
-- Program status registers
PSR_Inst:component PSR port map(
-- Global control signals
nRESET => nRESET,
CLK => CLK,
CLKEN => CLKEN,
-- ALU Data in
DataIn => ALU_DataOut,
PSRDInSel => PSR_PSRDInSel,
-- Current program state
CPSRIn => PSR_CPSRIn,
CPSRWrEn => PSR_CPSRWrEn,
CPSROut => PSR_CPSROut,
CFlForMul => PSR_CFlForMul,
-- Saved program state
SPSRIn => PSR_SPSRIn,
SPSROut => PSR_SPSROut,
SPSRWrMsk => PSR_SPSRWrMsk,
-- PSR mode control
PSRMode => PSR_PSRMode
);
IPDR_Inst:component IPDR port map(
-- Clock and reset
nRESET => nRESET,
CLK => CLK,
CLKEN => CLKEN,
-- Memory interface
RDATA => RDATA,
ABORT => ABORT,
-- Thumb decoder interface
ToThumbDecoder => IPDR_ToThumbDecoder,
FromThumbDecoder => IPDR_FromThumbDecoder,
HalfWordAddress => IPDR_HalfWordAddress,
-- Interfaces for the internal CPU modules
InstForDecode => IPDR_InstForDecode,
InstFetchAbort => IPDR_InstFetchAbort,
ADDRLow => ADDR_Int(1 downto 0),
StagnatePipeline => IPDR_StagnatePipeline,
StagnatePipelineDel => IPDR_StagnatePipelineDel,
FirstInstFetch => IPRD_FirstInstFetch,
-- Data out register and control(sign/zero, byte/halfword extension)
DataOut => IPDR_DataOut,
SignExt => IPDR_SignExt,
ZeroExt => IPDR_ZeroExt,
nB_HW => IPDR_nB_HW,
-- Immediate fields out
SExtOffset24Bit => IPDR_SExtOffset24Bit,
Offset12Bit => IPDR_Offset12Bit,
Offset8Bit => IPDR_Offset8Bit,
Immediate8Bit => IPDR_Immediate8Bit,
-- Bus control
EndianMode => IPDR_EndianMode
);
-- Address register and incrementer
AddressMUX_Incrementer_Inst:component AddressMux_Incrementer port map(
-- Clock and reset
nRESET => nRESET,
CLK => CLK,
CLKEN => CLKEN,
-- Address and control
ADDR => ADDR_Int,
FromPC => RegFile_PCOut, -- From register file
ToPC => RegFile_PCIn, -- To register file
FromALU => RBM_DataOut, -- From ALU *
ExceptionVector => AMI_ExceptionVector, -- From control logic
PCInSel => AMI_PCInSel,
ALUInSel => AMI_ALUInSel,
ExceptionVectorSel => AMI_ExceptionVectorSel,
PCIncStep => AMI_PCIncStep,
AdrIncStep => AMI_AdrIncStep,
AdrToPCSel => AMI_AdrToPCSel,
AdrCntEn => AMI_AdrCntEn
);
-- Data out register
DataOutMux_Inst:component DataOutMux port map(
-- Control signals
StoreHalfWord => DOR_StoreHalfWord, -- From control logic
StoreByte => DOR_StoreByte, -- From control logic
BigEndianMode => BigEndianMode, -- From control logic
-- Data signals
DataIn => RegFile_BBusOut, -- From the register file
WDATA => WDATA -- Output of the core
);
-- Register for shift amount
ShiftAmountReg_Inst:component ShiftAmountReg port map(
-- Clock and reset
nRESET => nRESET,
CLK => CLK,
CLKEN => CLKEN,
-- Data signals
ShLenRsIn => RegFile_ABusOut(7 downto 0), -- From register file
ShLenRsOut => Shifter_ShLenRs -- To shifter
);
-- A bus multiplexer
ABusMultiplexer_Inst:component ABusMultiplexer port map(
-- Data input
RegFileAOut => RegFile_ABusOut,
MultiplierAOut => Mult_ADataOut,
CPSROut => PSR_CPSROut,
SPSROut => PSR_SPSROut,
-- Control
RegFileAOutSel => ABM_RegFileAOutSel,
MultiplierAOutSel => ABM_MultiplierAOutSel,
CPSROutSel => ABM_CPSROutSel,
SPSROutSel => ABM_SPSROutSel,
-- Data output
ABusOut => ABM_ABusOut
);
-- B bus multiplexer
BBusMultiplexer_Inst:component BBusMultiplexer port map(
-- Data input
RegFileBOut => RegFile_BBusOut,
MultiplierBOut => Mult_BDataOut,
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