?? snds.a
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/*************************************************************************/
/* */
/* FILE NAME VERSION */
/* */
/* snds.a SNDS100 Board version 1.0 */
/* */
/* COMPONENT */
/* */
/* DESCRIPTION */
/* */
/* SNDS100 for KS32C5000, KS32C50100 ASSEBLER SYSTEM HEADER FILE */
/* */
/* AUTHOR */
/* */
/* */
/* DATA STRUCTURES */
/* */
/* */
/* FUNCTIONS */
/* */
/* DEPENDENCIES */
/* */
/* */
/*************************************************************************/
/*************************************************************************/
/* Format of the Program Status Register */
/*************************************************************************/
/* */
/* 31 30 29 28 7 6 5 4 3 2 1 0 */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
/*| N | Z | C | V | | I | F | T | M4 ~ M0 | */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
/* */
/* Processor Mode and Mask */
/* */
/*************************************************************************/
.equ FBit, +0x40
.equ IBit, +0x80
.equ LOCKOUT, +0xC0 /*Interrupt lockout value*/
.equ LOCK_MSK, +0xC0 /*Interrupt lockout mask value*/
.equ MODE_MASK, +0x1F /*Processor Mode Mask*/
.equ UDF_MODE, +0x1B /*Undefine Mode(UDF)*/
.equ ABT_MODE, +0x17 /*Abort Mode(ABT)*/
.equ SUP_MODE, +0x13 /*Supervisor Mode (SVC)*/
.equ IRQ_MODE, +0x12 /*Interrupt Mode (IRQ)*/
.equ FIQ_MODE, +0x11 /*Fast Interrupt Mode (FIQ)*/
.equ USR_MODE, +0x10 /*User Mode(USR)*/
/*************************************************************************/
/* SYSTEM STACK MEMORY : 8K bytes system stacks are defined at memory.a
/*************************************************************************/
.equ USR_STACK_SIZE, 1024
.equ UDF_STACK_SIZE, 512
.equ ABT_STACK_SIZE, 512
.equ IRQ_STACK_SIZE, 2048
.equ FIQ_STACK_SIZE, 2048
.equ SUP_STACK_SIZE, 2048
/*************************************************************************/
/* SYSTEM USER STACK MEMORY
/*************************************************************************/
.equ SYSTEM_SIZE, 1024 /*Define the system stack size*/
.equ TIMER_SIZE, 1024 /*Define timer HISR stack size*/
.equ TIMER_PRIORITY, 2 /*Timer HISR priority (values from*/
/* 0 to 2, where 0 is highest)*/
/*************************************************************************/
/* SYSTEM CLOCK */
/*************************************************************************/
.equ MHz, 1000000
/*ifdef KS32C50100*/
.equ fMCLK_MHz, 50000000 /*50MHz, KS32C50100*/
/*else
/*fMCLK_MHz 20000000 # 33MHz, KS32C5000
/*fMCLK_MHz 25000000 # 33MHz, KS32C5000
/*fMCLK_MHz 30000000 # 33MHz, KS32C5000
/*fMCLK_MHz 33000000 # 33MHz, KS32C5000
/*fMCLK_MHz 40000000 # 33MHz, KS32C5000
/*#endif*/
.equ fMCLK, fMCLK_MHz/MHz
/*************************************************************************/
/* SYSTEM MEMORY CONTROL REGISTER TABLES */
/*************************************************************************/
/* -> EXTDBWTH : Memory Bus Width register */
/*-------------------------------------------------------------*/
.equ DSR0, 2<<0 /*ROM0, 0 : Disable*/
/* 1 : Byte*/
/* 2 : Half-Word*/
/* 3 : Word*/
.equ DSR1, 2<<2 /* ROM1*/
.equ DSR2, 3<<4 /* ROM2*/
.equ DSR3, 3<<6 /* ROM3*/
.equ DSR4, 3<<8 /* ROM4*/
.equ DSR5, 3<<10 /* ROM5*/
.equ DSD0, 3<<12 /* DRAM0*/
.equ DSD1, 3<<14 /* DRAM1*/
.equ DSD2, 3<<16 /* DRAM2*/
.equ DSD3, 3<<18 /* DRAM3*/
.equ DSX0, 3<<20 /* EXTIO0*/
.equ DSX1, 3<<22 /* EXTIO1*/
.equ DSX2, 3<<24 /* EXTIO2*/
.equ DSX3, 3<<26 /* EXTIO3*/
.equ rEXTDBWTH, DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3
/*-------------------------------------------------------------*/
/* -> ROMCON0 : ROM Bank0 Control register */
/*-------------------------------------------------------------*/
.equ ROMBasePtr0, 0x000<<10 /*=0x0000000 */
.equ ROMEndPtr0, 0x020<<20 /*=0x0200000 */
.equ ROMBasePtr0_S, 0x100<<10 /*=0x1000000 #REMAP */
.equ ROMEndPtr0_S, 0x120<<20 /*=0x1200000 */
.equ PMC0, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page*/
.equ rTpa0, (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc0, (0x6<<4) /* 0x0=Disable, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle*/
/* 0x4=5Cycle, 0x5=6Cycle*/
/* 0x6=7Cycle, 0x7=Reserved*/
.equ rROMCON0, ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0
.equ rROMCON0_S, ROMEndPtr0_S+ROMBasePtr0_S+rTacc0+rTpa0+PMC0
/*-------------------------------------------------------------*/
/* -> ROMCON1 : ROM Bank1 Control register */
/*-------------------------------------------------------------*/
.equ ROMBasePtr1, 0x020<<10 /*=0x0200000*/
.equ ROMEndPtr1, 0x040<<20 /*=0x0400000*/
.equ ROMBasePtr1_S, 0x120<<10 /*=0x1200000*/
.equ ROMEndPtr1_S, 0x140<<20 /*=0x1400000*/
.equ PMC1, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page*/
.equ rTpa1, (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc1, (0x4<<4) /* 0x0=Disable, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle*/
/* 0x4=5Cycle, 0x5=6Cycle*/
/* 0x6=7Cycle, 0x7=Reserved*/
.equ rROMCON1, ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1
.equ rROMCON1_S, ROMEndPtr1_S+ROMBasePtr1_S+rTacc1+rTpa1+PMC1
/*-------------------------------------------------------------*/
/* -> ROMCON2 : ROM Bank2 Control register */
/*-------------------------------------------------------------*/
.equ ROMBasePtr2, 0x040<<10 /*=0x0400000*/
.equ ROMEndPtr2, 0x060<<20 /*=0x0600000 */
.equ ROMBasePtr2_S, 0x140<<10 /*=0x1400000 */
.equ ROMEndPtr2_S, 0x160<<20 /*=0x1600000 */
.equ PMC2, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page*/
/* 0x2=8Word Page, 0x3=16Word Page*/
.equ rTpa2, (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc2, (0x4<<4) /* 0x0=Disable, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle*/
/* 0x4=5Cycle, 0x5=6Cycle*/
/* 0x6=7Cycle, 0x7=Reserved*/
.equ rROMCON2, ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2
.equ rROMCON2_S, ROMEndPtr2_S+ROMBasePtr2_S+rTacc2+rTpa2+PMC2
/*-------------------------------------------------------------*/
/* -> ROMCON3 : ROM Bank3 Control register */
/*-------------------------------------------------------------*/
.equ ROMBasePtr3, 0x060<<10 /*=0x0600000 */
.equ ROMEndPtr3, 0x080<<20 /*=0x0800000 */
.equ ROMBasePtr3_S, 0x060<<10 /*=0x1600000 */
.equ ROMEndPtr3_S, 0x080<<20 /*=0x1800000 */
.equ PMC3, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page*/
.equ rTpa3, (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc3, (0x2<<4) /* 0x0=Disable, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle*/
/* 0x4=5Cycle, 0x5=6Cycle*/
/* 0x6=7Cycle, 0x7=Reserved*/
.equ rROMCON3, ROMEndPtr3+ROMBasePtr3+rTacc3+rTpa3+PMC3
.equ rROMCON3_S, ROMEndPtr3_S+ROMBasePtr3_S+rTacc3+rTpa3+PMC3
/*-------------------------------------------------------------*/
/* -> ROMCON4 : ROM Bank4 Control register */
/*-------------------------------------------------------------*/
.equ ROMBasePtr4, 0x080<<10 /*=0x0800000 */
.equ ROMEndPtr4, 0x0A0<<20 /*=0x0A00000 */
.equ ROMBasePtr4_S, 0x180<<10 /*=0x1800000 */
.equ ROMEndPtr4_S, 0x1A0<<20 /*=0x1A00000 */
.equ PMC4, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page*/
.equ rTpa4, (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc4, (0x4<<4) /* 0x0=Disable, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle*/
/* 0x4=5Cycle, 0x5=6Cycle*/
/* 0x6=7Cycle, 0x7=Reserved*/
.equ rROMCON4, ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC4
.equ rROMCON4_S, ROMEndPtr4_S+ROMBasePtr4_S+rTacc4+rTpa4+PMC4
/*-------------------------------------------------------------*/
/* -> ROMCON5 : ROM Bank5 Control register */
/*-------------------------------------------------------------*/
.equ ROMBasePtr5, 0x0A0<<10 /*=0x0A00000 */
.equ ROMEndPtr5, 0x0C0<<20 /*=0x0C00000 */
.equ ROMBasePtr5_S, 0x1A0<<10 /*=0x1A00000 */
.equ ROMEndPtr5_S, 0x1C0<<20 /*=0x1C00000 */
.equ PMC5, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page*/
.equ rTpa5, (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle */
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