?? snds.a
字號:
.equ rTacc5, (0x4<<4) /* 0x0=Disable, 0x1=2Cycle*/
/* 0x2=3Cycle, 0x3=4Cycle*/
/* 0x4=5Cycle, 0x5=6Cycle*/
/* 0x6=7Cycle, 0x7=Reserved*/
.equ rROMCON5, ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5
.equ rROMCON5_S, ROMEndPtr5_S+ROMBasePtr5_S+rTacc5+rTpa5+PMC5
/*-------------------------------------------------------------*/
/* -> DRAMCON0 : RAM Bank0 control register */
/*-------------------------------------------------------------*/
.equ EDO_Mode0, 1 /*(EDO)0=Normal, 1=EDO DRAM*/
.equ CasPrechargeTime0, 0 /*(Tcp)0=1cycle,1=2cycle*/
.equ CasStrobeTime0, 1 /*(Tcs)0=1cycle ~ 3=4cycle*/
.equ DRAMCON0Reserved, 1 /* Must be set to 1*/
.equ RAS2CASDelay0, 0 /*(Trc)0=1cycle,1=2cycle*/
.equ RASPrechargeTime0, 2 /*(Trp)0=1cycle ~ 3=4clcyle*/
.equ DRAMBasePtr0, 0x100<<10 /*=0x1000000 */
.equ DRAMEndPtr0, 0x140<<20 /*=0x1200000 */
.equ DRAMBasePtr0_S, 0x000<<10 /*=0x0000000 /*# REMAP*/
.equ DRAMEndPtr0_S, 0x040<<20 /*=0x0200000 */
.equ NoColumnAddr0, 2 /*0=8bit,1=9bit,2=10bit,3=11bits*/
/*-------------------------------------------------------------*/
.equ Tcs0, CasStrobeTime0<<1
.equ Tcp0, CasPrechargeTime0<<3
.equ dumy0, DRAMCON0Reserved<<4 /* dummy cycle*/
.equ Trc0, RAS2CASDelay0<<7
.equ Trp0, RASPrechargeTime0<<8
.equ CAN0, NoColumnAddr0<<30
.equ rDRAMCON0, CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
.equ rDRAMCON0_S, CAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
/*----------------------------------------------------------------------------------*/
.equ SRAS2CASDelay0, 1 /*(Trc)0=1cycle,1=2cycle*/
.equ SRASPrechargeTime0, 3 /*(Trp)0=1cycle ~ 3=4clcyle*/
.equ SNoColumnAddr0, 0 /*0=8bit,1=9bit,2=10bit,3=11bits*/
.equ SCAN0, SNoColumnAddr0<<30
.equ STrc0, SRAS2CASDelay0<<7
.equ STrp0, SRASPrechargeTime0<<8
.equ rSDRAMCON0, SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0
.equ rSDRAMCON0_S, SCAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+STrp0+STrc0
/*-------------------------------------------------------------*/
/* -> DRAMCON1 : RAM Bank1 control register */
/*-------------------------------------------------------------*/
.equ EDO_Mode1, 1 /*(EDO)0=Normal, 1=EDO DRAM*/
.equ CasPrechargeTime1, 0 /*(Tcp)0=1cycle,1=2cycle*/
.equ CasStrobeTime1, 1 /*(Tcs)0=1cycle ~ 3=4cycle*/
.equ DRAMCON1Reserved, 0 /* Must be set to 1*/
.equ RAS2CASDelay1, 0 /*(Trc)0=1cycle,1=2cycle*/
.equ RASPrechargeTime1, 0 /*(Trp)0=1cycle ~ 3=4clcyle*/
.equ DRAMBasePtr1, 0x140<<10 /*=0x12000000 */
.equ DRAMEndPtr1, 0x180<<20 /*=0x14000000 */
.equ DRAMBasePtr1_S, 0x040<<10 /*=0x04000000 */
.equ DRAMEndPtr1_S, 0x080<<20 /*=0x08000000 */
.equ NoColumnAddr1, 2 /*0=8bit,1=9bit,2=10bit,3=11bits*/
/*-------------------------------------------------------------*/
.equ Tcs1, CasStrobeTime1<<1
.equ Tcp1, CasPrechargeTime1<<3
.equ dumy1, DRAMCON1Reserved<<4 /* dummy cycle*/
.equ Trc1, RAS2CASDelay1<<7
.equ Trp1, RASPrechargeTime1<<8
.equ CAN1, NoColumnAddr1<<30
.equ rDRAMCON1, CAN1+DRAMEndPtr1+DRAMBasePtr1+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1
.equ rDRAMCON1_S, CAN1+DRAMEndPtr1_S+DRAMBasePtr1_S+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1
.equ SRAS2CASDelay1, 1 /*(Trc)0=1cycle,1=2cycle*/
.equ SRASPrechargeTime1, 1 /*(Trp)0=1cycle ~ 3=4clcyle*/
.equ SNoColumnAddr1, 0 /*0=8bit,1=9bit,2=10bit,3=11bits*/
.equ SCAN1, SNoColumnAddr1<<30
.equ STrc1, SRAS2CASDelay1<<7
.equ STrp1, SRASPrechargeTime1<<8
.equ rSDRAMCON1, SCAN1+DRAMEndPtr1+DRAMBasePtr1+STrp1+STrc1
.equ rSDRAMCON1_S, SCAN1+DRAMEndPtr1_S+DRAMBasePtr1_S+STrp1+STrc1
/* -> DRAMCON2 : RAM Bank2 control register */
/*-------------------------------------------------------------*/
.equ EDO_Mode2, 0 /*(EDO)0=Normal, 1=EDO DRAM*/
.equ CasPrechargeTime2, 0 /*(Tcp)0=1cycle,1=2cycle*/
.equ CasStrobeTime2, 1 /*(Tcs)0=1cycle ~ 3=4cycle*/
.equ DRAMCON2Reserved, 1 /* Must be set to 1*/
.equ RAS2CASDelay2, 0 /*(Trc)0=1cycle,1=2cycle*/
.equ RASPrechargeTime2, 0 /*(Trp)0=1cycle ~ 3=4clcyle*/
.equ DRAMBasePtr2, 0x180<<10 /*=0x14000000 */
.equ DRAMEndPtr2, 0x1C0<<20 /*=0x18000000 */
.equ DRAMBasePtr2_S, 0x080<<10 /*=0x08000000 */
.equ DRAMEndPtr2_S, 0x0C0<<20 /*=0x0C000000 */
.equ NoColumnAddr2, 2 /*0=8bit,1=9bit,2=10bit,3=11bits*/
/*-------------------------------------------------------------*/
.equ Tcs2, CasStrobeTime2<<1
.equ Tcp2, CasPrechargeTime2<<3
.equ dumy2, DRAMCON2Reserved<<4 /* dummy cycle*/
.equ Trc2, RAS2CASDelay2<<7
.equ Trp2, RASPrechargeTime2<<8
.equ CAN2, NoColumnAddr2<<30
.equ rDRAMCON2, CAN2+DRAMEndPtr2+DRAMBasePtr2+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2
.equ rDRAMCON2_S, CAN2+DRAMEndPtr2_S+DRAMBasePtr2_S+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2
/*--------------------------*/
.equ SRAS2CASDelay2, 1 /*(Trc)0=1cycle,1=2cycle*/
.equ SRASPrechargeTime2, 1 /*(Trp)0=1cycle ~ 3=4clcyle*/
.equ SNoColumnAddr2, 0 /*0=8bit,1=9bit,2=10bit,3=11bits*/
.equ SCAN2, SNoColumnAddr2<<30
.equ STrc2, SRAS2CASDelay2<<7
.equ STrp2, SRASPrechargeTime2<<8
.equ rSDRAMCON2, SCAN2+DRAMEndPtr2+DRAMBasePtr2+STrp2+STrc2
.equ rSDRAMCON2_S, SCAN2+DRAMEndPtr2_S+DRAMBasePtr2_S+STrp2+STrc2
/*-------------------------------------------------------------*/
/* -> DRAMCON3 : RAM Bank3 control register */
/*-------------------------------------------------------------*/
.equ EDO_Mode3, 0 /*(EDO)0=Normal, 1=EDO DRAM*/
.equ CasPrechargeTime3, 0 /*(Tcp)0=1cycle,1=2cycle*/
.equ CasStrobeTime3, 1 /*(Tcs)0=1cycle ~ 3=4cycle*/
.equ DRAMCON3Reserved, 1 /* Must be set to 1*/
.equ RAS2CASDelay3, 0 /*(Trc)0=1cycle,1=2cycle*/
.equ RASPrechargeTime3, 0 /*(Trp)0=1cycle ~ 3=4clcyle*/
.equ DRAMBasePtr3, 0x1C0<<10 /*=0x14000000 */
.equ DRAMEndPtr3, 0x200<<20 /*=0x18000000 */
.equ DRAMBasePtr3_S, 0x0C0<<10 /*=0x0C000000 */
.equ DRAMEndPtr3_S, 0x100<<20 /*=0x10000000 */
.equ NoColumnAddr3, 2 /*0=8bit,1=9bit,=10bit,3=11bits*/
/*-------------------------------------------------------------*/
.equ Tcs3, CasStrobeTime3<<1
.equ Tcp3, CasPrechargeTime3<<3
.equ dumy3, DRAMCON3Reserved<<4 /* dummy cycle*/
.equ Trc3, RAS2CASDelay3<<7
.equ Trp3, RASPrechargeTime3<<8
.equ CAN3, NoColumnAddr3<<30
.equ rDRAMCON3, CAN3+DRAMEndPtr3+DRAMBasePtr3+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3
.equ rDRAMCON3_S, CAN3+DRAMEndPtr3_S+DRAMBasePtr3_S+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3
/*--------------------------*/
.equ SRAS2CASDelay3, 1 /*(Trc)0=1cycle,1=2cycle*/
.equ SRASPrechargeTime3, 1 /*(Trp)0=1cycle ~ 3=4clcyle*/
.equ SNoColumnAddr3, 0 /*0=8bit,1=9bit,2=10bit,3=11bits*/
.equ SCAN3, SNoColumnAddr3<<30
.equ STrc3, SRAS2CASDelay3<<7
.equ STrp3, SRASPrechargeTime3<<8
.equ rSDRAMCON3, SCAN3+DRAMEndPtr3+DRAMBasePtr3+STrp3+STrc3
.equ rSDRAMCON3_S, SCAN3+DRAMEndPtr3_S+DRAMBasePtr3_S+STrp3+STrc3
/*-------------------------------------------------------------*/
/* -> REFEXTCON : External I/O & Memory Refresh cycle Control Register */
/*-------------------------------------------------------------*/
.equ RefCycle, 16 /*Unit [us], 1k refresh 16ms*/
.equ CASSetupTime, 0 /*0=1cycle, 1=2cycle*/
.equ CASHoldTime, 0 /*0=1cycle, 1=2cycle, 2=3cycle,*/
/*3=4cycle, 4=5cycle,*/
.equ RefCycleValue, ((2048+1-(RefCycle*fMCLK))<<21)
.equ Tcsr, (CASSetupTime<<20) /* 1cycle*/
.equ Tcs, (CASHoldTime<<17)
.equ ExtIOBase, 0x18360 /* Refresh enable, VSF=1*/
.equ rREFEXTCON, RefCycleValue+Tcsr+Tcs+ExtIOBase
/*-------------------------------------------------------------*/
/*SRefCycle, 16 #Unit [us], 4k refresh 64ms*/
.equ SRefCycle, 8 /*Unit [us], 4k refresh 64ms*/
.equ ROWcycleTime, 3 /*0=1cycle, 1=2cycle, 2=3cycle,*/
/*3=4cycle, 4=5cycle,*/
.equ SRefCycleValue, ((2048+1-(SRefCycle*fMCLK))<<21)
.equ STrc, (ROWcycleTime<<17)
.equ rSREFEXTCON, SRefCycleValue+STrc+ExtIOBase
/*-------------------------------------------------------------*/
/*************************************************************************/
/* KS32C50100 SPECIAL REGISTERS */
/*************************************************************************/
.equ ASIC_BASE, 0x3ff0000
/* Interrupt Control */
.equ INT_CNTRL_BASE, ASIC_BASE+0x4000 /*Define base of all interrupt*/
/* controller registers*/
.equ IntMode, ASIC_BASE+0x4000
.equ IntPend, ASIC_BASE+0x4004
.equ IntMask, ASIC_BASE+0x4008
.equ INTOFFSET, ASIC_BASE+0x4024
/* I/O Port Interface */
.equ IOPMODE, ASIC_BASE+0x5000
.equ IOPCON, ASIC_BASE+0x5004
.equ IOPDATA, ASIC_BASE+0x5008
/* UART 0,1 */
.equ UARTLCON0, ASIC_BASE+0xD000
.equ UARTCONT0, ASIC_BASE+0xD004
.equ UARTSTAT0, ASIC_BASE+0xD008
.equ UARTTXH0, ASIC_BASE+0xD00C
.equ UARTRXB0, ASIC_BASE+0xD010
.equ UARTBRD0, ASIC_BASE+0xD014
.equ UARTLCON1, ASIC_BASE+0xE000
.equ UARTCONT1, ASIC_BASE+0xE004
.equ UARTSTAT1, ASIC_BASE+0xE008
.equ UARTTXH1, ASIC_BASE+0xE00C
.equ UARTRXB1, ASIC_BASE+0xE010
.equ UARTBRD1, ASIC_BASE+0xE014
/* TIMER 0,1 */
.equ TIMER_BASE, ASIC_BASE+0x6000 /*Define base for all timer*/
/* registers*/
/*===============================================================*/
/* Setup for SNDS100 Start-up Dialog */
/*===============================================================*/
/***************************************************************/
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