?? hdllib.ref
字號:
EN myuartcore NULL "D:/Project/Xilinx Project/My_Own/MyUart/MyUartCore.vhd" sub00/vhpl06 1352726412
EN recv NULL "D:/Project/Xilinx Project/My_Own/MyUart/recv.vhd" sub00/vhpl04 1352726410
AR myuartcore behavioral "D:/Project/Xilinx Project/My_Own/MyUart/MyUartCore.vhd" sub00/vhpl07 1352726413
EN trans_4_to_8 NULL "D:/Project/Xilinx Project/My_Own/MyUart/trans_4_to_8.vhd" sub00/vhpl08 1352726414
EN top NULL "D:/Project/Xilinx Project/My_Own/MyUart/top.vhd" sub00/vhpl10 1352726418
AR trans_4_to_8 behavioral "D:/Project/Xilinx Project/My_Own/MyUart/trans_4_to_8.vhd" sub00/vhpl09 1352726415
EN debounce_circut NULL "D:/Project/Xilinx Project/My_Own/MyUart/debounce_circut.vhd" sub00/vhpl14 1352726416
AR baud_gen behavioral "D:/Project/Xilinx Project/My_Own/MyUart/baud_gen.vhd" sub00/vhpl01 1352726407
AR debounce_circut behavioral "D:/Project/Xilinx Project/My_Own/MyUart/debounce_circut.vhd" sub00/vhpl15 1352726417
AR keydwn_check behavioral "D:/Project/Xilinx Project/My_Own/MyUart/keydwn_check.vhd" sub00/vhpl13 1352561415
EN keydwn_check NULL "D:/Project/Xilinx Project/My_Own/MyUart/keydwn_check.vhd" sub00/vhpl12 1352561414
AR transfer behavioral "D:/Project/Xilinx Project/My_Own/MyUart/transfer.vhd" sub00/vhpl03 1352726409
AR top behavioral "D:/Project/Xilinx Project/My_Own/MyUart/top.vhd" sub00/vhpl11 1352726419
EN transfer NULL "D:/Project/Xilinx Project/My_Own/MyUart/transfer.vhd" sub00/vhpl02 1352726408
AR recv behavioral "D:/Project/Xilinx Project/My_Own/MyUart/recv.vhd" sub00/vhpl05 1352726411
EN baud_gen NULL "D:/Project/Xilinx Project/My_Own/MyUart/baud_gen.vhd" sub00/vhpl00 1352726406
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