?? mcp2510.h
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/********************************************************************
*
* Standard register and bit definitions for the Microchip
* MCP2510 Stand-Alone CAN Controller.
*
* This file supports assembler and C/EC++ development for
* MSP430x13x devices.
*
********************************************************************/
#ifndef __mcp2510
#define __mcp2510
#define uchar unsigned char
#define uint unsigned int
#define ulong unsigned long
#define mcpCS0 BIT0 //P3OUT
#define mcpCS1 BIT6 //P3OUT
#define WDI BIT7 //P3OUT
#define RST0 BIT7 //P2OUT
#define RST1 BIT5 //P3OUT
//***************** MCP Commands on SPI *****************
#define RESET (0xc0) // Reset internal registers to default state, set config mode
#define RTS (0x80) // Trigg transmission
#define RD_STAT (0xA0) // Start reading status
#define BIT_MOD (0x05) // Bit modify command data == MASK, BITS
#define READ (0x03) // Read data from memory
#define WRITE (0x02) // Write data to memory
#define DUMMY (0x55)
/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/
#define BFPCTRL (0x0C) /*** RXNBF PIN CONTROL AND STATUS REGISTER ***/
#define B0BFM (0x01) // 1 = Pin is used as interrupt when valid message loaded into RXBx
#define B1BFM (0x02) // 0 = Digital output mode
#define B0BFE (0x04) // 1 = Pin function enabled, operation mode determined by BxBFM bit
#define B1BFE (0x08) // 0 = Pin function disabled, pin goes to high impedance state
#define B0BFS (0x10) // Reads as ‘0’ when RX1BF is configured as interrupt pin
#define B1BFS (0x20) // RX1BF Pin State (digital output mode only)
#define TXRTSCTRL (0x0D) /*** TXNRTS PIN CONTROL AND STATUS REGISTER ***/
#define B0RTSM (0x01) // 1 = Pin is used to request message transmission of TXBx buffer (on falling edge)
#define B1RTSM (0x02) // 0 = Digital inpu
#define B2RTSM (0x04)
#define B0RTS (0x08) // TXxRTS Pin State
#define B1RTS (0x10) // Reads state of TX1RTS pin when in digital input mode
#define B2RTS (0x20) // Reads as ‘0’ when pin is in ‘request to send’ mode
#define CANSTAT (0x0E) /*** CAN STATUS REGISTER ***/
#define ICOD0 (0x02) // Interrupt Flag Code
#define ICOD1 (0x04)
#define ICOD2 (0x08)
#define INT_NO (0x00) // No Interrupt
#define INT_ERR (0x02) // Error Interrupt
#define INT_WP (0x04) // Wake Up Interrupt
#define INT_TXB0 (0x06) // TXB0 Interrupt
#define INT_TXB1 (0x08) // TXB1 Interrupt
#define INT_TXB2 (0x0A) // TXB2 Interrupt
#define INT_RXB0 (0x0C) // RXB0 Interrupt
#define INT_RXB1 (0x0E) // RXB1 Interrupt
#define OPMOD0 (0x20) // Operation Mode
#define OPMOD1 (0x40)
#define OPMOD2 (0x80)
#define OPM_NORMAL (0x00) // Device is in Normal Operation Mode
#define OPM_SLEEP (0x20) // Device is in Sleep Mode
#define OPM_LOOP (0x40) // Device is in Loopback Mode
#define OPM_LISTEN (0x60) // Device is in Listen Only Mode
#define OPM_CONFIG (0x80) // Device is in Configuration Mode
#define CANCTRL (0x0F) /*** CAN CONTROL REGISTER ***/
#define CLKPRE0 (0x01) // CLKOUT Pin Prescaler
#define CLKPRE1 (0x02)
#define CLKF_MB1 (0x00) // FCLKOUT = System Clock/1
#define CLKF_MB2 (0x01) // FCLKOUT = System Clock/2
#define CLKF_MB4 (0x02) // FCLKOUT = System Clock/4
#define CLKF_MB8 (0x03) // FCLKOUT = System Clock/8
#define CLKEN (0x04) // CLKOUT Pin Enable:1 = CLKOUT pin enabled;
// 0 = CLKOUT pin disabled (Pin is in high impedance state)
#define ABAT (0x10) // Abort All Pending Transmissions:1 = Request abort of all pending transmit buffers
// 0 = Terminate request to abort all transmissions
#define REQOP0 (0x20) // Request Operation Mode
#define REQOP1 (0x40)
#define REQOP2 (0x80)
#define RQM_NORMAL (0x00) // Set Normal Operation Mode
#define RQM_SLEEP (0x20) // Set Sleep Mode
#define RQM_LOOP (0x40) // Set Loopback Mode
#define RQM_LISTEN (0x60) // Set Listen Only Mode
#define RQM_CONFIG (0x80) // Set Configuration Mode
#define TEC (0x1C) /*** TRANSMITTER ERROR COUNTER ***/
#define REC (0x1D) /*** RECEIVER ERROR COUNTER ***/
#define CNF1 (0x2A) /*** CONFIGURATION REGISTER 1 ***/
#define BRP0 (0x01) // Baud Rate Prescaler
#define BRP1 (0x02) // TQ = 2 x (BRP + 1) / FOSC
#define BRP2 (0x04)
#define BRP3 (0x08)
#define BRP4 (0x10)
#define BRP5 (0x20)
#define SJW0 (0x40) // Synchronization Jump Width Length
#define SJW1 (0x80) // 11 = Length = 4 x TQ;10 = Length = 3 x TQ
// 01 = Length = 2 x TQ;00 = Length = 1 x TQ
#define CNF2 (0x29) /*** CONFIGURATION REGISTER 2 ***/
#define PRSEG0 (0x01) // Propagation Segment Length:(PRSEG + 1) x TQ
#define PRSEG1 (0x02)
#define PRSEG2 (0x04)
#define PHSEG10 (0x08) // Phase Segment 1 Length:(PHSEG1 + 1) x TQ
#define PHSEG11 (0x10)
#define PHSEG12 (0x20)
#define SAM (0x40) // 1 = Bus line is sampled three times at the sample point
// 0 = Bus line is sampled once at the sample point
#define BTLMODE (0x80) // 1 = Length of Phase Seg 2 determined by PHSEG22:PHSEG20 bits of CNF3
// 0 = Length of Phase Seg 2 is the greater of Phase Seg 1 and IPT (2TQ)
#define CNF3 (0x28) /*** CONFIGURATION REGISTER 3 ***/
#define PHSEG20 (0x01) // PHSEG2<2:0>:Phase Segment 2 Length;(PHSEG2 + 1) x TQ
#define PHSEG21 (0x02)
#define PHSEG22 (0x04)
#define WAKFIL (0x40) // 1 = Wake-up filter enabled;0 = Wake-up filter disabled
#define CANINTE (0x2B) /*** INTERRUPT ENABLE REGISTER ***/
#define RX0IE (0x01) // Receive Buffer 0 Full Interrupt Enable
// 1 = Interrupt on error during message reception or transmission
// 0 = Disabled
#define RX1IE (0x02) // Receive Buffer 1 Full Interrupt Enable
#define TX0IE (0x04) // Transmit Buffer 0 Empty Interrupt Enable
#define TX1IE (0x08) // Transmit Buffer 1 Empty Interrupt Enable
#define TX2IE (0x10) // Transmit Buffer 2 Empty Interrupt Enable
#define ERRIE (0x20) // Error Interrupt Enable
#define WAKIE (0x40) // Wakeup Interrupt Enable
#define MERRE (0x80) // Message Error Interrupt Enable
#define CANINTF (0x2C) /*** INTERRUPT FLAG REGISTER ***/
#define RX0IF (0x01) // Receive Buffer 0 Full Interrupt Flag
// 1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
// 0 = No interrupt pending
#define RX1IF (0x02) // Receive Buffer 1 Full Interrupt Flag
#define TX0IF (0x04) // Transmit Buffer 0 Empty Interrupt Flag
#define TX1IF (0x08) // Transmit Buffer 1 Empty Interrupt Flag
#define TX2IF (0x10) // Transmit Buffer 2 Empty Interrupt Flag
#define ERRIF (0x20) // Error Interrupt Flag
#define WAKIF (0x40) // Wakeup Interrupt Flag
#define MERRF (0x80) // Message Error Interrupt Flag
#define EFLG (0x2D) /*** ERROR FLAG REGISTER ***/
#define EWARN (0x01) // Error Warning Flag
// -- Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)
// -- Reset when both REC and TEC are less than 96
#define RXWAR (0x02) // Receive Error Warning Flag
// -- Set when REC is equal to or greater than 96
// -- Reset when REC is less than 96
#define TXWAR (0x04) // Transmit Error Warning Flag
// -- Set when TEC is equal to or greater than 96
// -- Reset when TEC is less than 96
#define RXEP (0x08) // Receive Error-Passive Flag
// -- Set when REC is equal to or greater than 128
// -- Reset when REC is less than 128
#define TXEP (0x10) // Transmit Error-Passive Flag
// -- Set when TEC is equal to or greater than 128
// -- Reset when TEC is less than 128
#define TXBO (0x20) // Bus-Off Error Flag
// -- Bit set when TEC reaches 255
// -- Reset after a successful bus recovery sequence
#define RX0OVR (0x40) // Receive Buffer 0 Overflow Flag
// -- Set when a valid message is received for RXB0 and CANINTF.RX0IF = 1
// -- Must be reset by MCU
#define RX1OVR (0x80) // Receive Buffer 1 Overflow Flag
// -- Set when a valid message is received for RXB1 and CANINTF.RX1IF = 1
// -- Must be reset by MCU
/*******************************Transmit BUFFER 0 REGISTERS******************************************************/
#define TXB0CTRL (0x30) /*** Transmit Buffer 0 Control Register ***/
#define TXP0 (0x01) // TXP<1:0>: Transmit Buffer Priority
#define TXP1 (0x02) // --11 = Highest Message Priority
// --10 = High Intermediate Message Priority
// --11 = Low Intermediate Message Priority
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