#ifndef AT91C_TYPES_INC
#define AT91C_TYPES_INC

typedef volatile unsigned int AT91_REG;

typedef struct _AT91S_EMAC
{
	AT91_REG	 EMAC_CTL; 	/* Network Control Register */
	AT91_REG	 EMAC_CFG; 	/* Network Configuration Register */
	AT91_REG	 EMAC_SR; 	/* Network Status Register */
	AT91_REG	 EMAC_TAR; 	/* Transmit Address Register */
	AT91_REG	 EMAC_TCR; 	/* Transmit Control Register */
	AT91_REG	 EMAC_TSR; 	/* Transmit Status Register */
	AT91_REG	 EMAC_RBQP; 	/* Receive Buffer Queue Pointer */
	AT91_REG	 Reserved0[1]; 	/*  */
	AT91_REG	 EMAC_RSR; 	/* Receive Status Register */
	AT91_REG	 EMAC_ISR; 	/* Interrupt Status Register */
	AT91_REG	 EMAC_IER; 	/* Interrupt Enable Register */
	AT91_REG	 EMAC_IDR; 	/* Interrupt Disable Register */
	AT91_REG	 EMAC_IMR; 	/* Interrupt Mask Register */
	AT91_REG	 EMAC_MAN; 	/* PHY Maintenance Register */
	AT91_REG	 Reserved1[2]; 	/*  */
	AT91_REG	 EMAC_FRA; 	/* Frames Transmitted OK Register */
	AT91_REG	 EMAC_SCOL; 	/* Single Collision Frame Register */
	AT91_REG	 EMAC_MCOL; 	/* Multiple Collision Frame Register */
	AT91_REG	 EMAC_OK; 	/* Frames Received OK Register */
	AT91_REG	 EMAC_SEQE; 	/* Frame Check Sequence Error Register */
	AT91_REG	 EMAC_ALE; 	/* Alignment Error Register */
	AT91_REG	 EMAC_DTE; 	/* Deferred Transmission Frame Register */
	AT91_REG	 EMAC_LCOL; 	/* Late Collision Register */
	AT91_REG	 EMAC_ECOL; 	/* Excessive Collision Register */
	AT91_REG	 EMAC_CSE; 	/* Carrier Sense Error Register */
	AT91_REG	 EMAC_TUE; 	/* Transmit Underrun Error Register */
	AT91_REG	 EMAC_CDE; 	/* Code Error Register */
	AT91_REG	 EMAC_ELR; 	/* Excessive Length Error Register */
	AT91_REG	 EMAC_RJB; 	/* Receive Jabber Register */
	AT91_REG	 EMAC_USF; 	/* Undersize Frame Register */
	AT91_REG	 EMAC_SQEE; 	/* SQE Test Error Register */
	AT91_REG	 EMAC_DRFC; 	/* Discarded RX Frame Register */
	AT91_REG	 Reserved2[3]; 	/*  */
	AT91_REG	 EMAC_HSH; 	/* Hash Address High[63:32] */
	AT91_REG	 EMAC_HSL; 	/* Hash Address Low[31:0] */
	AT91_REG	 EMAC_SA1L; 	/* Specific Address 1 Low, First 4 bytes */
	AT91_REG	 EMAC_SA1H; 	/* Specific Address 1 High, Last 2 bytes */
	AT91_REG	 EMAC_SA2L; 	/* Specific Address 2 Low, First 4 bytes */
	AT91_REG	 EMAC_SA2H; 	/* Specific Address 2 High, Last 2 bytes */
	AT91_REG	 EMAC_SA3L; 	/* Specific Address 3 Low, First 4 bytes */
	AT91_REG	 EMAC_SA3H; 	/* Specific Address 3 High, Last 2 bytes */
	AT91_REG	 EMAC_SA4L; 	/* Specific Address 4 Low, First 4 bytes */
	AT91_REG	 EMAC_SA4H; 	/* Specific Address 4 High, Last 2 bytesr */
} AT91S_EMAC, *AT91PS_EMAC;

#endif