'\" t.so wrs.an.\" ads860/target.nr - Motorola MPC8xx(F)ADS target specific documentation.\".\" Copyright 1984-1996 Wind River Systems, Inc..\".\" modification history.\" --------------------.\" 01a,08jul02,dtr  Modifying loadf address parameter. SPR 63545.\" 01m,28jan02,dtr  Removed references to netif...\" 01m,07nov01,dtr  Update info about TFFS..\" 01m,25oct01,dtr  Removed reference to dataCachePatch.obj and ROM_RESIDENT bootroms now work so removed comment from know problems..\" 01l,23oct01,dtr  Changed comment about EDO_DRAM. SPR 9254.\" 01k,23aug01,dgp  changed manual entry to reference entry per SPR 23698.\" 01j,27aug99,stv  updated documentation (SPR# 26269). .\" 01i,19mar99,cn   added information on sysMotCpmEnd (SPR# 25839)..\" 01h,01mar99,cn   added information on known problems/limitations..\" 01g,22feb99,cn   added information on 8xx Errata and data cache patch..\" 01f,30jan99,cn   updated documentation (SPR# 8746 and SPR# 20751).\" 01e,28apr98,yp   added info on TFFS..\" 01d,25nov97,map  added info on 860 devices used..\" 01c,12sep97,map  info about problems with the "go" command.\" 01b,24jul96,tpr  added Aux Clock Doc + corrected typo..\" 01a,16jun96,tpr  created from mv1604..\".\".TH "ads860" T "Motorola MPC821/860ADS and MPC8xxFADS" "Rev: 17 Jun 96" "VXWORKS REFERENCE MANUAL".SH "NAME".aX "Motorola MPC821/860ADS & MPC8xxFADS ".SH "INTRODUCTION"This note provides board-specific information necessary to runVxWorks.  Before running VxWorks, verify that the board runs in thefactory configuration.The ads860 BSP produces a VxWorks image running on either the PowerPC 8xx processors. From the VxWorks perspective these processors are equivalent.The URL: http://www.mot.com/SPS/RISC/netcomm/support/index.html#errata_group provides information on all MPC8xx, MPC860T, and MPC860SAR device errata from Rev. A onwards.  Please, check which ones apply to your particular device/revision before using VxWorks. WRS has not implemented any of the workarounds suggested there for any of the known hardware problems..SH "BOOT ROMS"No VxWorks Boot ROM is provided with this BSP release. Nevertheless VxWorksboot code is working if downloaded into the SIMM Flash ROM.To program the SIMM Flash ROM, the ADI card from Motorola is required.This debug card is available for Sun workstation or PC. Connect this ADI cardto the MPC821/860ADS board via the ADI port. Check that a 12V potential isprovided to the MPC8xx(F)ADS board; otherwise the SIMM Flash will not be erasedand/or re-programmed. On the host, start the mpc8bug executable (mpc8bug.exe onPC). Once the prompt appears, reset the board with the following command:.CS	821Bug> reset:h.CEThen download the bootrom_uncmp.hex file to the Flash:	821Bug> loadf /<PATH_TO_THE_ADS860_BSP>/bootrom_uncmp.hex 10000The 100000 value is the address in DRAM memory where the bootrom_uncmp.hexfile is temporarily downloaded before it is moved to Flash. A messagelike the following copy should appear:.CS	loadf: Loading Srecords file . . .	Loading flash mapped sections to ram memory buffer:	Loading block : at 00100000 		      : 0004efd0 bytes loaded	Programming flash : 0004efd0 bytes  at 02800100-0284f0cf 	Flash programming completed 	Loading ram mapped sections to ram memory:	Entry point (IP) is not set 	Heap start address set to 0284f0d0	821Bug> .CENow the SIMM Flash memory is programmed with the new boot program. To executethis new boot program turn the board off and on. If the board is still connected to the ADI card then the processor is stopped at the first instructionto execute. From the mpc8bug prompt call the "go" command to resume FLASHcode execution..SH "Jumpers"No jumpers are relevant to VxWorks configuration. However, the dip switch DS1on the FADS8xxDB Daughter Board should not be changed from its factory configuration, otherewise erratic behaviour of the LXT970 , which implements the physical layer device for the FEC, may derive. See also "SpecialConsiderations" below. .PPThis board doesn't have non-volatile RAM; thus boot parametersare not preserved when the system is powered off..PPTo load VxWorks, and for more information, follow the instructions in the"Getting Started"chapter of the.I "VxWorks Programmer's Guide.".PPAn alternative way to load vxWorks is through the ADI debug card. Plug the ADIconnector in the ADI port of the board, power on the board and start thempc8bug executable on the host. Execute the reset command to initialize theboard:.CS	821Bug> reset:h.CEThen download VxWorks:.CS	821Bug> load /<ADS860_BSP_PATH>/vxWorks	Loading ELF file . . .	Entry point set to 00010000	Loading section 1 (.text) : 0005fcec bytes at 00010000 	Loading section 2 (.rodata) : 0000263c bytes at 0015fcec 	Loading section 4 (.data) : 00001058 bytes at 00162328 	Loading section 5 (.got) : 00000010 bytes at 00163380 	Loading section 7 (.sbss) : 00000298 bytes at 00163390 (not loaded)	Loading section 8 (.bss) : 000079e8 bytes at 00163628 (not loaded)	Heap start address set to 0016b010	Loaded 000008da symbols into the symbol table	Duplicated symbols (-103) expanded with enumerated suffixes 	r3 and r5 are set to 0.CEThen reset the DER register .CS	821Bug> rms DER 0.CEAnd finally start VxWorks execution:.CS	821Bug> go 10000.CEOn some ADI configurations, resuming execution with the "go" couldresult in exceptions or other problems. In such cases, unplug the ADIconnector, and reset the target board to start VxWorks.	.PP.SH "TrueFFS support".PPThis BSP supports the optional product TrueFFS for Tornado. To use TrueFFSinstall the product and define INCLUDE_TFFS in config.h. TrueFFS is set up to use the PCMCIA slots and the half of the Flash SIMM thatis not used by the bootrom as drives for use with dosFs.If you use the function tffsBootImagePut, the "offset parameter should becomputed as (ROM_TEXT_ADRS - ROM_BASE_ADRS) and should evaluate to 0x100 for the default configuration. The boot-image (i.e. bootrom, bootrom_uncmpetc) should be filtered using objcopyppc and converted to binary prior to using tffsBootImagePut..PP.SH "DEVICES".PPThe chip drivers included are:    ppc860Timer.c - Timer library for PPC decrementer, CPM timers 2,3,4    ppc860Sio.o	  - Serial Communications library for SMC UART    ppc860Intr.c  - Programmable Interrupt Controller Library    motCpmEnd.o	  - END-style Ethernet Communication library for SCC    motFecEnd.o	  - END-style Fast-Ethernet Controller Communication library		    for MPC860DB daughter-boards with MPC860T & MPC860P                    microprocessor    sysMotCpmEnd.c- configuration module for motCpmEnd driver.PPThe timer driver, ppc860Timer, implements a system clock using the PPCdecrementer timer, an auxiliary clock using CPM timer 2, and a 32-bittimestamp facilty by cascading CPM timers 3 & 4. The BSP configures SMC1 as a UART to implement a console device and the CPM SCC1 as an ethernet port. The name `cpm' should be specified as the boot device to the boot ROMs when booting vxWorks over that interface. To disable the CPM SCC1,undefine the macro INCLUDE_CPM_END in the file config.h.On MPC860DB daughter-boards with MPC860T & MPC860P microprocessor, the Fast Ethernet Controller (FEC) makes available fast Ethernet connectivity through the use of a MII-compliant physical device and a RJ45 connector.Support for those board is granted if the macro FADS_860T or FADS_860P is defined in config.h. In this case, the FEC will be used as the default network interface, while the CPM SCC1 will be disabled. However, the user may enable either interfaces, and even the configuration where both of them are exploited is supported. Each time config.h is edited, new vxWorksand bootrom images should be built and Flash memory is to be programmed.If the user wishes to use the FEC as the boot device, the string `motfec' should be specified in the boot string..PP.SH "SPECIAL CONSIDERATIONS".PPThe DRAM controller setup is only performed by the boot program. VxWorksdoesn't re-initialize the DRAM controller when it is executed.The DRAM memory controller initialization code can recognize boththe size and type of the DRAM plugged and its access time..PPTo increase performance in high operation frequencies, on FADS8xx boards,the on-board SDRAM bank may be used as the local system memory. However,the only supported configuration is the one with the clock speed above32 Mhz., and only for late revisions of the silicon. More to the point,MPC860T processors with Rev. mask lower than B3 and date code earlier than 9832, or MPC860EN with Rev. lower than B1 and date code earlier than 9829, are not garanteed to work with the same UPM tables (see romInit.s). In order to configure the system to initialize the SDRAM, define the macro INCLUDE_SDRAM in config.h. Both the SDRAM banks and the regular DRAM SIMM are mapped to the lower memory addressing space of the processor, and therefore they cannot be used at the same time. If the user wishes to do so, this bsp has to be modified..PPThis bsp no longer defaults to disable both instruction and data cache when the macro EDO_DRAM is defined in config.h. Motorola claims the problem only occurs on early revisions of ADS860 and FADS8xx boards.To remove cache support undefine USER_I_CACHE_ENABLE, USER_D_CACHE_ENABLE  and INCLUDE_CACHE_SUPPORT in config.h..PPSome early revisions of MPC821 and MPC850 lack the ability of supportingthe timestamp driver, since they only feature two internal timers, whereasthe timestamp driver uses timer 3 and timer 4 in cascade mode. On these processors, the timestamp library support is not available..PPSupport to the second serial channel (SMC) is not available on boards using either an MPC823 or an MPC850. In this case, the configuration module for theserial driver only initializes the first serial channel..PPThe module sysMotCpmEnd.c creates the load string for the END-style cpm interface. The Ethernet tranceiver on the FADS8xx boards is normally wiredto the SCC1 channel of the Communication Processor Module (CPM). However, on FADS823/850 boards, SCC2 is used instead. The module sysMotCpmEnd.c dinamically configures the driver to use either the SCC1 or the SCC2 channel by reading the BCSR3 register to find out which processor is being used and set up the load string accordingly. The user does not need to perform anyother configuration, unless he wants to change default parameters..PPThe MPC8xx(F)ADS boards do not have a unique Ethernet hardwareaddress assigned to each board.  A unique address is absolutely necessary ifthe user wishes to connect the board to a network.  Thus, the usermust provide a suitable 6 byte Ethernet address for each board usedon a network.  The address is programmed by changing the sysCpmEnetAddrcharacter array in the file sysLib.c.  The first three bytes (0x08, 0x00, 0x3e)are a Motorola-specific prefix that should be kept as-is.  The user mustchange the last three bytes from 0x03, 0x02, 0x01 to three unique bytes(i.e., bytes not used by any other Motorola Ethernet connection on your net).Check with your system administrator if you do not know this information.If these bytes need changing (they often will not), a new boot ROMmust be burned, and a new image must be built.Likewise, the sysFecEnetAddr character array in the file sysLib.c must provide a suitable 6 byte Ethernet address for each board where the FEC is used. The user must change the last three bytes from 0x03, 0x02,0x02 to three unique bytes that are not used on any other Motorola connection on the user's network. Check with your system administrator if you do not know this information. If these bytes need changing (they often will not), a new boot ROM must be burned, and a new image must be built..PPThe MC68160 EEST part is very sensitive to its input power voltage (VDD).VDD to the chip must be between 4.75 and 5.25; values outside thisrange may diminish functionality.  Therefore, the power supplied to thetarget board and the chip should be checked carefully.  Note that theremay be a significant voltage drop between the power supply connectorsand the chip (the fuses and connectors alone cause approximately a0.1 volts drop).In order to get the Ethernet device to work properly the processor clock (PLL)should be at least 24 megahertz. Both the boot program and VxWorks setthe processor clock to 24 megahertz. Configurations with processors runningat a frequency higher than 24 megahertz or lower than 20 megahertz were nottested. .PPThe driver for the FEC exploits the MII Management Interface as describedin the IEEE802.3 standard. In order to do so, it assumes that the auto-negotiation function bit MF0 on the on-board dip switch DS1 is in the OFF condition. In this configuration, which is also the default one, the PHY can advertise its technical abilities and its link may be dynamically established in software.  The reference entry for the FEC driver explains how the process to establish a valid physical link for this device may be affected by the user settings.  However, if the above MF0 bit is not in the default configuration, the driver may fail to initialize the link. Nevertheless, the user may write his own media initialization routine and set the function pointer _func_motFecPhyInit to the address of this routine. See the referenceentry motFecEnd for more information..PPThe problems associated with the data cache libraries are now defunct so the dataCachePatch.obj has been removed from the BSP..PP.SS "Known Problems"A hardware problem causes corruption of some registers and results in occasional lockup on boot. This occurs only when the Keep Alive Power source is connected to a backup battery. A S/W workaround has been included which reduces the possiblity of this problem occuring. It can be included by defining USE_KEY_REGS in config.h.  .SH "SEE ALSO".pG "Getting Started, Configuration"