/* sysAta.c - LoPEC ATA-2 initialization for sysLib.c *//* Copyright 1984-1998 Wind River Systems, Inc. *//* Copyright 1997,1998,2000,2001 Motorola, Inc. All Rights Reserved */#include "copyright_wrs.h"/*modification history--------------------01a,06dec00,cak  ported to LoPEC from (01f mcp750) *//* DescriptionThis file contains the sysAtaInit() necessary forinitializing the ATA/EIDE subsystem. *//* includes */#include "vxWorks.h"#include "config.h"#ifdef	INCLUDE_ATA/* local defines */#define PCI_TARGET_MASK		0xFFFFFFFC	/* mask out AD[1:0] */#define PCI_CFG_CHIP_ENABLE_ADR	0x40		/* IDE Chip Enable Register */#define PCI_CFG_CHIP_ENABLE	0x03		/* IDE Chip Enable Value *//* external declarations *//* global declarations *//* function declarations *//******************************************************************************** sysAtaInit - initialize the EIDE/ATA interface** Perform the necessary initialization required before starting up the* ATA/EIDE driver.*/void sysAtaInit    (    int         pciBusNo,    int         pciDevNo,    int         pciFuncNo    )    {    int         baseAddr;    int         chipEnable;    /*     * Disable PCI device by clearing its control (command) register     * in its configuration header.     */    pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0);    /*     * Don't re-locate the BARs, use the default (ISA Legacy) addresses     * No code required     */    /* Configure Cache Line Size Register to max value */    pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_CACHE_LINE_SIZE,                      8);    /* Configure Latency Timer to max value */    pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER,                      PCI_LAT_TIMER);    /*     * Configure device control (command) register to enable Bus Master     * (for future DMA capability) and I/O Space.     */    pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND,                      (UINT16)(PCI_CMD_MASTER_ENABLE | PCI_CMD_IO_ENABLE));    /* Get and save Base Address of Command Reg for Primary Controller */    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_0,                        &baseAddr);    ataResources[0].resource.ioStart[0] = 		( ISA_MSTR_IO_LOCAL | (baseAddr & PCI_TARGET_MASK));    /*     * Get and save an adjusted Base Address of Control Reg for     * Primary Controller     */    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_1,                        &baseAddr);    ataResources[0].resource.ioStart[1] = 		( ISA_MSTR_IO_LOCAL | ((baseAddr & PCI_TARGET_MASK) + 2));    /*     * Initialize the remainder of the ataResources structure for the     * Primary Controller     */    ataResources[0].ctrlType = IDE_LOCAL;    ataResources[0].drives = 2;    ataResources[0].intVector = (int)IDE_CNTRLR0_INT_LVL;    ataResources[0].intLevel = (int)IDE_CNTRLR0_INT_LVL;    ataResources[0].configType = ( ATA_PIO_AUTO | ATA_GEO_PHYSICAL );    ataResources[0].semTimeout = 0;    ataResources[0].wdgTimeout = 0;    /* Get and save Base Address of Command Reg for Secondary Controller */    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_2,                        &baseAddr);    ataResources[1].resource.ioStart[0] = 		( ISA_MSTR_IO_LOCAL | (baseAddr & PCI_TARGET_MASK));    /*     * Get and save an adjusted Base Address of Control Reg for     * Secondary Controller     */    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_3,                        &baseAddr);    ataResources[1].resource.ioStart[1] = 		( ISA_MSTR_IO_LOCAL | ((baseAddr & PCI_TARGET_MASK) + 2));    /*     * Initialize the remainder of the ataResources structure for the     * Secondary Controller     */    ataResources[1].ctrlType = IDE_LOCAL;    ataResources[1].drives = 2;    ataResources[1].intVector = (int)IDE_CNTRLR1_INT_LVL;    ataResources[1].intLevel = (int)IDE_CNTRLR1_INT_LVL;    ataResources[1].configType = ( ATA_PIO_AUTO | ATA_GEO_PHYSICAL );    ataResources[1].semTimeout = 0;    ataResources[1].wdgTimeout = 0;    /* Enable IDE Primary and Secondary Channels */    pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_CHIP_ENABLE_ADR,                        &chipEnable);    pciConfigOutLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_CHIP_ENABLE_ADR,                        chipEnable | PCI_CFG_CHIP_ENABLE);    }#endif /* INCLUDE_ATA */