// DEMO.C : demonstrates implemented features

#pragma chip PIC18C242  // select device

// OTHER SAMPLE CODE:
// demo-ins.c : generating single instructions using C code
// demo-mat.c : integer math operations
// demo-fpm.c : floating point math
// demo-fxm.c : fixed point math
// demo-rom.c : const data and DW
// demo-ptr.c : indexed tables and pointers
// demo-var.c : defining RAM variables

#pragma rambank 0
char a0, b0;

#pragma rambank 1
char a1, b1;

#pragma rambank -
char a, bx;

bit bt1, bt;



// ************************************************
// ************************************************
// INTERRUPT SUPPORT

#include "int18XXX.h"

void _highPriorityInt(void);

#pragma origin 0x8
interrupt highPriorityIntServer(void)
{
    // W, STATUS and BSR are saved to shadow registers

    // handle the interrupt
    // 8 code words available including call and RETFIE
    _highPriorityInt();

    // restore W, STATUS and BSR from shadow registers
    #pragma fastMode
}

#pragma origin 0x18
interrupt lowPriorityIntServer(void)
{
    // W, STATUS and BSR are saved by the next macro.
    int_save_registers

    /* NOTE : shadow registers are updated, but will be
       overwritten in case of a high-priority interrupt.
       Therefore #pragma fastMode should not be used on
       low-priority interrupts. */

    // save remaining registers on demand (error/warning)
    //uns16 sv_FSR0 = FSR0;
    //uns16 sv_FSR1 = FSR1;
    //uns16 sv_FSR2 = FSR2;
    //uns8 sv_PCLATH = PCLATH;
    //uns8 sv_PCLATU = PCLATU;
    //uns8 sv_PRODL = PRODL;
    //uns8 sv_PRODH = PRODH;
    //uns24 sv_TBLPTR = TBLPTR;
    //uns8 sv_TABLAT = TABLAT;

    // handle the interrupt
    // ..

    // restore registers that are saved
    //FSR0 = sv_FSR0;
    //FSR1 = sv_FSR1;
    //FSR2 = sv_FSR2;
    //PCLATH = sv_PCLATH;
    //PCLATU = sv_PCLATU;
    //PRODL = sv_PRODL;
    //PRODH = sv_PRODH;
    //TBLPTR = sv_TBLPTR;
    //TABLAT = sv_TABLAT;

    int_restore_registers // W, STATUS and BSR
}

/* IMPORTANT : GIEH/GIE or GIEL should normally NOT be
   set or cleared in the interrupt routine. GIEH/GIEL are
   AUTOMATICALLY cleared on interrupt entry by the CPU
   and set to 1 on exit (by RETFIE). Setting GIEH/GIEL to
   1 inside the interrupt service routine will cause
   nested interrupts if an interrupt is pending. Too deep
   nesting may crash the program ! */


void _highPriorityInt(void)
{
    // save registers on demand

    // restore registers on demand
}




void subr( void)
{
    char a, bx, c, d;
    uns16 a16;
    uns16 b16 = a16;
    uns24 a24, b24;

    b24.high16 = a24.low16;

    a = bx;
    c = 10;
    a = 10 | bx | d;

    do  {
        nop();
        a --;
    } while ( --d > 0);

    a = bx * 100;
    a16 = (uns16)bx*c;

   #asm
    DW 0xFFFF   ; any data or instruction
    DW 0x0000
    DW /*CLRF*/ 0x6A00 + /*UNBANKED*/ 0x000 + /*PRODL*/ 0xF3
   #endasm
    PRODL = 0;
}


uns24 accumulate( void)
{
    uns16 i;
    uns24 rs = 0;

    // add all numbers from 1 to 1999
    for (i = 1; i < 2000; i++)
        rs += i;
    return rs;
}


void main(void)
{
    clearRAM();  // built in function

    subr();

    GIEL = 1;  // enable low priority interrupt
    GIEH = 1;  // enable high priority interrupt

    uns24 s = accumulate();

    bt1 = 0;     // clear bit
    a.7 = 1;     // set bit
    bt = !bt;    // bit toggle

    if (a > bx)
        a &= 0xF0;  // mask bits

    // uns16 is 16 bit (unsigned long)
    uns16 aa = 1000;  // local variable
    uns16 bb = aa+10000;
    aa |= 0x10F;  // set bits
    bb &= 0x7F;   // clear bits

    char i = 10;   // 8 bit unsigned

    aa -= i;

    uns24 acc24 = 0;  // 24 bit unsigned
    for (aa = 0; aa < 3000; aa++)  {
        acc24 += aa;
        nop();
    }

    if (acc24 == 0)
        acc24 = 0xFFFF;

    aa = i * 200;

    acc24 ++;  // increment
    aa --;     // decrement

    if (aa == 0  ||  !bt)
        a1 -= 33;
    if (!a.7)  // test single bit
        b0 += a1 + b1;

    nop();  // delay 1 instruction cycle

    // W and WREG is the same register (for compatibility)
    W = 10;
    WREG >>= 1;  // shift right
}