/* * linux/drivers/usbd/sa1100_bi/udc.c * * Copyright (c) 2000, 2001, 2002 Lineo * Copyright (c) 2001 Hewlett Packard * * By:  *      Stuart Lynne <sl@lineo.com>,  *      Tom Rushworth <tbr@lineo.com>,  *      Bruce Balden <balden@lineo.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * *//* * Please note that this driver works reasonably well with StrongARM parts * running at 206Mhz.  * * It is not possible to run the USB with DMA on the StrongARM running at 133Mhz. * Running without DMA is possible and reasonably reliable. This can be done by * restricting the USB packetsize to 16bytes for your bulk endpoints. */ #include <linux/config.h>#include <linux/module.h>#include "../usbd-export.h"#include "../usbd-build.h"#include "../usbd-module.h"MODULE_AUTHOR ("sl@lineo.com, tbr@lineo.com");MODULE_DESCRIPTION ("USB Device SA-1100 Bus Interface");USBD_MODULE_INFO ("sa1100_bi 0.2");#include <linux/kernel.h>#include <linux/slab.h>#include <linux/interrupt.h>#include <linux/pci.h>#include <linux/init.h>#include <linux/delay.h>#include <asm/atomic.h>#include <asm/io.h>#include <linux/proc_fs.h>#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,6)#define USE_ADD_DEL_TIMER_FOR_USBADDR_CHECK 1#include <linux/timer.h>#else#undef USE_ADD_DEL_TIMER_FOR_USBADDR_CHECK#include <linux/tqueue.h>#endif#include <linux/netdevice.h>#include <linux/version.h>#include <linux/pci.h>#include <linux/cache.h>#include <asm/dma.h>#include <asm/mach/dma.h>#include <asm/irq.h>#include <asm/system.h>#include <asm/hardware.h>#include <asm/types.h>#include <asm/uaccess.h>#include <asm/io.h>#include <asm/pgtable.h>#include <asm/pgalloc.h>#include "../usbd-debug.h"#include "../usbd.h"#include "../usbd-func.h"#include "../usbd-bus.h"#include "../usbd-inline.h"#include "usbd-bi.h"#include "sa1100.h"#if defined(CONFIG_SA1100_COLLIE)       // XXX change to 5500#include <asm-arm/arch-sa1100/collie.h>#include <asm/ucb1200.h>#include <asm/arch/tc35143.h>#endif#define MIN(a,b) ((a) < (b) ? (a) : (b))#define MAX(a,b) ((a) > (b) ? (a) : (b))#define ACTIVEA 1#define ACTIVEB 2static struct usb_device_instance *udc_device;	// required for the interrupt handler/* * ep_endpoints - map physical endpoints to logical endpoints */static struct usb_endpoint_instance *ep_endpoints[UDC_MAX_ENDPOINTS];//static struct urb ep0_urb;unsigned char usb_address;extern unsigned int udc_interrupts;extern unsigned int udc_interrupts_last;unsigned int ep0_interrupts;unsigned int tx_interrupts;unsigned int rx_interrupts;unsigned int sus_interrupts;unsigned int res_interrupts;unsigned int udc_address_errors;unsigned int udc_ticks;unsigned int udc_fixed;unsigned int ep0_interrupts_last;unsigned int rx_interrupts_last;unsigned int tx_interrupts_last;unsigned int udc_rpe_errors;unsigned int udc_ep1_errors;unsigned int udc_ep2_errors;unsigned int udc_ep2_tpe;unsigned int udc_ep2_tur;unsigned int udc_ep2_sst;unsigned int udc_ep2_fst;int usbd_rcv_dma;int usbd_tx_dma;static int udc_saw_sof;#ifdef USE_ADD_DEL_TIMER_FOR_USBADDR_CHECKstatic struct timer_list sa1100_usb_dev_addr_check;static int usb_addr_check_initialized = 0;#define CHECK_INTERVAL   1#elsestatic struct tq_struct sa1100_tq;#endif/* * DMA control register structure */typedef struct {	volatile u_long DDAR;	volatile u_long SetDCSR;	volatile u_long ClrDCSR;	volatile u_long RdDCSR;	volatile dma_addr_t DBSA;	volatile u_long DBTA;	volatile dma_addr_t DBSB;	volatile u_long DBTB;} dma_regs_t;/* ********************************************************************************************* *//* IO */volatile int udc (volatile unsigned int *regaddr){	volatile unsigned int value;	int ok;	for (ok = 1000, value = *(regaddr); value != *(regaddr) && ok--; value = *(regaddr));	if (!ok) {		dbg_udc (0, "NOT OK: %p %x", regaddr, value);	}	return value;}static __inline__ volatile int _udc (volatile unsigned int *regaddr){	volatile unsigned int value;	int ok;	for (ok = 1000, value = *(regaddr); value != *(regaddr) && ok--; value = *(regaddr));	if (!ok) {		printk (KERN_ERR "NOT OK: %p %x\n", regaddr, value);	}	return value;}static __inline__ void _sa1100_bi_dma_run (dmach_t channel, int active){	dma_regs_t *regs = (dma_regs_t *) io_p2v (_DDAR (channel));	if (active == ACTIVEA) {		regs->SetDCSR = DCSR_STRTA | DCSR_RUN;	} else {		regs->SetDCSR = DCSR_STRTB | DCSR_RUN;	}}static __inline__ int _sa1100_bi_dma_queue_buffer_irq (dmach_t channel, dma_addr_t data, int size){	int status;	dma_regs_t *regs = (dma_regs_t *) io_p2v (_DDAR (channel));	status = regs->RdDCSR;	if (((status & DCSR_BIU) && (status & DCSR_STRTB)) || (!(status & DCSR_BIU) && !(status & DCSR_STRTA))) {		regs->ClrDCSR = DCSR_DONEA | DCSR_STRTA;		regs->DBSA = data;		regs->DBTA = size;		// Once is good, twice is better....		regs->DBSA = data;		regs->DBTA = size;		return ACTIVEA;	} else {		regs->ClrDCSR = DCSR_DONEB | DCSR_STRTB;		regs->DBSB = data;		regs->DBTB = size;		// Once is good, twice is better....		regs->DBSB = data;		regs->DBTB = size;		return ACTIVEB;	}}static __inline__ int _sa1100_bi_dma_flush_all_irq (dmach_t channel){	dma_regs_t *regs = (dma_regs_t *) io_p2v (_DDAR (channel));	regs->ClrDCSR = DCSR_STRTA | DCSR_STRTB | DCSR_RUN | DCSR_IE;	return 0;}static __inline__ int _sa1100_bi_dma_stop_get_current_irq (dmach_t channel, dma_addr_t * addr, int active){	dma_regs_t *regs = (dma_regs_t *) io_p2v (_DDAR (channel));	// addr sometimes can be set incorrectly, the caller must do bounds checking	switch (active) {	case ACTIVEA:		regs->ClrDCSR = DCSR_RUN | DCSR_STRTA | DCSR_RUN | DCSR_IE;		*addr = regs->DBSA;	// not reliable		return 0;	case ACTIVEB:		regs->ClrDCSR = DCSR_RUN | DCSR_STRTB | DCSR_RUN | DCSR_IE;		*addr = regs->DBSB;	// not reliable		return 0;	default:		*addr = 0;		return -ENXIO;	}}/* ********************************************************************************************* */static u32 getCPUID (char **stepping){	u32 cpuID;	__asm__ __volatile__ (" mrc   p15, 0, %0, c0, c0":"=r" (cpuID)			      :);	if (NULL != stepping) {		switch (cpuID & 0xf) {		case 0:			*stepping = "A0";			break;		case 4:			*stepping = "B0";			break;		case 5:			*stepping = "B1";			break;		case 6:			*stepping = "B2";			break;		case 8:			*stepping = "B4";			break;		case 9:			*stepping = "B5";			break;		default:			*stepping = "??";			dbg_udc (0, "stepping unknown, ID#%x", (cpuID & 0xf));		}	}	return (cpuID);}void udc_fix_errata_29 (char *msg){	int ok;	u32 cpuID;		// from init.c	cpuID = getCPUID (NULL);	// Set errata 29 fix bit, if possible	if (cpuID == 0 || (cpuID & 0xF) >= 9) {		// Unknown CPU, or B5 stepping and above		// set errata 29 fix enable (for B5 and above, B4 will ignore)		int udc_cr;		for (ok = 10; ok > 0; ok--) {			*(UDCCR) |= /*UDCCR_ERR29 */ 0x80;			// Do some dummy reads....			udc_cr = *(UDCCR);			udc_cr = *(UDCCR);			udc_cr = *(UDCCR);			if (udc (UDCCR) & /*UDCCR_ERR29 */ 0x80) {				dbg_udc (0,					 "%s: set errata 29 fix bit worked, UDCCR#%02x ok=%d cpuID#%08x",					 msg, udc (UDCCR), ok, cpuID);				ok = -2;				break;			}		}		if (ok != -2) {			dbg_udc (0, "%s: set errata 29 fix bit failed, UDCCR#%02x ok=%d cpuID#%08x",				 msg, udc (UDCCR), ok, cpuID);		}	} else {		dbg_udc (0, "%s: errata 29 fix bit not available, cpuID#%08x", msg, cpuID);	}}/* ********************************************************************************************* *//** * sa1100_tick - clock timer task  * @data: *   * Run from global clock tick to check if we are suspended. */#ifdef USE_ADD_DEL_TIMER_FOR_USBADDR_CHECKstatic void sa1100_tick (unsigned long data)#elsestatic void sa1100_tick (void *data)#endif{	udc_ticks++;	// is driver active	if (data) {		if (_udc (UDCAR) != usb_address) {			dbg_udc (0, "sa1100_tick: ADDRESS ERROR DETECTED %02x %02x", *(UDCAR), usb_address);			udc_address_errors++;			udc_fixed++;		}		*(UDCAR) = usb_address;		// re-queue task#ifdef USE_ADD_DEL_TIMER_FOR_USBADDR_CHECK		sa1100_usb_dev_addr_check.expires = jiffies + CHECK_INTERVAL;		add_timer (&sa1100_usb_dev_addr_check);#else		queue_task (&sa1100_tq, &tq_timer);#endif	}}/* ********************************************************************************************* *//* Interrupt Handler *//** * int_hndlr_cable - interrupt handler for cable */static void int_hndlr_cable (int irq, void *dev_id, struct pt_regs *regs){#ifdef CONFIG_SA1100_USBCABLE_GPIO	dbg_udc (1, "udc_cradle_interrupt:");	udc_cable_event ();#endif}/** * int_hndlr_device - interrupt handler * */static void int_hndlr_device (int irq, void *dev_id, struct pt_regs *regs){	unsigned int status;	status = *(UDCSR);	*(UDCSR) = status;	udc_interrupts++;	//dbg_udc(0, "");	dbg_intr(2, "[%d]: CSR: %02x CCR: %02x CAR: %02x:%02x", udc_interrupts, status, *(UDCCR), *(UDCAR), usb_address);	// Handle common interrupts first, IN (tx) and OUT (recv)	if (status & UDCSR_RIR) {		ep1_int_hndlr (status);	}	if (status & UDCSR_TIR) {		ep2_int_hndlr (status, 1);	}	// handle less common interrupts	if (status & (UDCSR_EIR | UDCSR_RSTIR | UDCSR_SUSIR | UDCSR_RESIR)) {		if (status & UDCSR_EIR) {			ep0_int_hndlr (status);		}		if (status & UDCSR_RSTIR) {			dbg_intr (1, "[%d] DEVICE_RESET: CSR: %02x CS0: %02x CAR: %02x",                                         udc_interrupts, *(UDCSR), *(UDCCS0), *(UDCAR));			usbd_device_event (udc_device, DEVICE_RESET, 0);		}		if (status & UDCSR_SUSIR) {			dbg_intr (1, "[%d] SUSPEND address: %02x irq: %02x status: %02x",                                         udc_interrupts, *(UDCAR), irq, status);			sus_interrupts++;#if defined(CONFIG_SA1100_COLLIE)	// XXX change to 5500			usbd_device_event (udc_device, DEVICE_BUS_INACTIVE, 0);#else			usbd_device_event (udc_device, DEVICE_BUS_INACTIVE, 0);			//usbd_device_event (udc_device, DEVICE_RESET, 0);#endif			udc_suspended_interrupts (udc_device);			udc_ticker_poke ();		}		if (status & UDCSR_RESIR) {			dbg_intr (1, "[%d] RESUME address: %02x irq: %02x status: %02x", udc_interrupts, *(UDCAR), irq, status);                        *(UDCAR) = usb_address;			res_interrupts++;#if defined(CONFIG_SA1100_COLLIE)	// XXX change to 5500			usbd_device_event (udc_device, DEVICE_BUS_ACTIVITY, 0);#endif			udc_all_interrupts (udc_device);			udc_ticker_poke ();		}	}	// Check that the UDC has not forgotton it's address, force it back to correct value	//if (_udc (UDCAR) != usb_address) {	//	udc_address_errors++;	//}	*(UDCAR) = usb_address;}/* ********************************************************************************************* *//* * Start of public functions. *//** * udc_init - initialize * * Return non-zero if we cannot see device. **/int udc_init (void){	// reset	return 0;}/** * udc_start_in_irq - start transmit * @endpoint: * * Called with interrupts disabled. */void udc_start_in_irq (struct usb_endpoint_instance *endpoint){	ep2_int_hndlr (0, 0);}void udc_stall_ep0 (void){	int ok = 0;	// QQQ eh?	dbg_udc (0, "stalling ep0 (UDCCS0_FST,UDCCS0_FST,UDCCS0_SST)");	// write 1 to set FST	SET_AND_TEST ((*(UDCCS0) &= UDCCS0_FST), !(udc (UDCCS0) & UDCCS0_FST), ok);	if (!ok) {		dbg_udc (0, "cannot stall !(UDCCS0&UDCCS0_FST) UDCCS0: %02x", *(UDCCS0));	}	// write 0 to reset FST	SET_AND_TEST ((*(UDCCS0) &= ~UDCCS0_FST), (udc (UDCCS0) & UDCCS0_FST), ok);	if (!ok) {		dbg_udc (0, "cannot stall (UDCCS0&UDCCS0_FST) UDCCS0: %02x", *(UDCCS0));	}	// write 1 to reset SST	SET_AND_TEST ((*(UDCCS0) = UDCCS0_SST), (udc (UDCCS0) & UDCCS0_SST), ok);	if (!ok) {		dbg_udc (0, "cannot stall (UDCCS0&UDCCS0_SST) UDCCS0: %02x", *(UDCCS0));	}}static void stall_ep_n (int ep, volatile unsigned int *regaddr, int fst){	int ok;	dbg_udc (0, "stalling ep %d (FST)", ep);	// write 1 to set FST	SET_AND_TEST ((*(regaddr) = fst), !(udc (regaddr) & fst), ok);	if (!ok) {		dbg_udc (0, "cannot stall !(reg&fst) UDCCS%d: %02x", ep, *(regaddr));	}}static void reset_ep_n (int ep, volatile unsigned int *regaddr, int fst, int sst){	int ok;	dbg_udc (1, "reset ep %d (FST)", ep);	// write 0 to reset FST	SET_AND_TEST ((*(regaddr) &= ~fst), (udc (regaddr) & fst), ok);	if (!ok) {		dbg_udc (0, "cannot stall !(reg&fst) UDCCS%d: %02x", ep, *(regaddr));	}	// write 1 to reset SST	SET_AND_TEST ((*(regaddr) = sst), (udc (regaddr) & sst), ok);	if (!ok) {		dbg_udc (0, "cannot stall (reg&sst) UDCCS%d: %02x", ep, *(UDCCS0));	}}/** * udc_stall_ep - stall endpoint * @ep: physical endpoint * * Stall the endpoint. */void udc_stall_ep (unsigned int ep){	dbg_udc (0, "STALLING %d (FST)", ep);	switch (ep) {	case 1:		stall_ep_n (1, UDCCS1, UDCCS1_FST);		break;	case 2:		stall_ep_n (2, UDCCS2, UDCCS2_FST);		break;	}}/** * udc_reset_ep - reset endpoint * @ep: physical endpoint * reset the endpoint. * * returns : 0 if ok, -1 otherwise */void udc_reset_ep (unsigned int ep){	dbg_udc (1, "RESETING %d (FST)", ep);	switch (ep) {	case 0:		reset_ep_n (1, UDCCS0, UDCCS0_FST, UDCCS0_SST);		break;	case 1:		reset_ep_n (1, UDCCS1, UDCCS1_FST, UDCCS1_SST);		break;	case 2:		reset_ep_n (2, UDCCS2, UDCCS2_FST, UDCCS2_SST);		break;	}}