Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    list_pathout_ports_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Nov 26, 1998  02:33:30
Verilog_XL_Turbo_NT 2.6.9   Nov 26, 1998  02:33:30

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Compiling source file "list_pathout_ports_test.v"
Highest level modules:
test


Module addbit
  Port sum is connected to a path delay output
  Port sum is connected to a path delay output
  Port co is connected to a path delay output
L23 "list_pathout_ports_test.v": $finish at simulation time 2
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.7 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Nov 26, 1998  02:33:31