?? invoke_options_test.log
字號:
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
invoke_options_test.v
+a
+b
-f invoke_options_test1.f
+a1
+b1
-f invoke_options_test2.f
+a2
+b2
+test2
+c2
+c1
+c
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 8, 1998 01:55:34
Verilog_XL_Turbo_NT 2.6.9 Dec 8, 1998 01:55:34
Copyright (c) 1995 Cadence Design Systems, Inc. All Rights Reserved.
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Copyright (c) 1995 UNIX Systems Laboratories, Inc. Reproduced with Permission.
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AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.
Cadence Design Systems, Inc.
555 River Oaks Parkway
San Jose, California 95134
For technical assistance please contact the Cadence Response Center at
1-800-CADENC2 or send email to crc_customers@cadence.com
For more information on Cadence's Verilog-XL product line send email to
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Compiling source file "invoke_options_test.v"
Highest level modules:
test
C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
invoke_options_test.v
+a
+b
-f
invoke_options_test1.f
+a1
+b1
-f
invoke_options_test2.f
+a2
+b2
+test2
+c2
+c1
+c
Simulation was NOT invoked with a +test1 option
C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
invoke_options_test.v
+a
+b
-f
invoke_options_test1.f
+a1
+b1
-f
invoke_options_test2.f
+a2
+b2
+test2
+c2
+c1
+c
Simulation WAS invoked with a +test2 option
L33 "invoke_options_test.v": $finish at simulation time 1
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.8 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9 Dec 8, 1998 01:55:35
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