Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    read_vecval_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Nov 26, 1998  21:40:22
Verilog_XL_Turbo_NT 2.6.9   Nov 26, 1998  21:40:22

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Compiling source file "read_vecval_test.v"
Highest level modules:
test


Vector data encoded value:
  bit[ 0]  aval/bval = 1/0  4-state value = 1
  bit[ 1]  aval/bval = 0/0  4-state value = 0
  bit[ 2]  aval/bval = 0/0  4-state value = 0
  bit[ 3]  aval/bval = 0/0  4-state value = 0
  bit[ 4]  aval/bval = 0/0  4-state value = 0
  bit[ 5]  aval/bval = 0/0  4-state value = 0
  bit[ 6]  aval/bval = 0/0  4-state value = 0
  bit[ 7]  aval/bval = 0/0  4-state value = 0
  bit[ 8]  aval/bval = 0/0  4-state value = 0
  bit[ 9]  aval/bval = 0/0  4-state value = 0
  bit[10]  aval/bval = 0/0  4-state value = 0
  bit[11]  aval/bval = 0/0  4-state value = 0
  bit[12]  aval/bval = 0/0  4-state value = 0
  bit[13]  aval/bval = 0/0  4-state value = 0
  bit[14]  aval/bval = 0/0  4-state value = 0
  bit[15]  aval/bval = 0/0  4-state value = 0
  bit[16]  aval/bval = 0/1  4-state value = z
  bit[17]  aval/bval = 0/0  4-state value = 0
  bit[18]  aval/bval = 0/0  4-state value = 0
  bit[19]  aval/bval = 0/0  4-state value = 0
  bit[20]  aval/bval = 0/0  4-state value = 0
  bit[21]  aval/bval = 0/0  4-state value = 0
  bit[22]  aval/bval = 0/0  4-state value = 0
  bit[23]  aval/bval = 0/0  4-state value = 0
  bit[24]  aval/bval = 0/0  4-state value = 0
  bit[25]  aval/bval = 0/0  4-state value = 0
  bit[26]  aval/bval = 0/0  4-state value = 0
  bit[27]  aval/bval = 0/0  4-state value = 0
  bit[28]  aval/bval = 0/0  4-state value = 0
  bit[29]  aval/bval = 0/0  4-state value = 0
  bit[30]  aval/bval = 0/0  4-state value = 0
  bit[31]  aval/bval = 0/0  4-state value = 0
  bit[32]  aval/bval = 0/0  4-state value = 0
  bit[33]  aval/bval = 0/0  4-state value = 0
  bit[34]  aval/bval = 0/0  4-state value = 0
  bit[35]  aval/bval = 0/0  4-state value = 0
  bit[36]  aval/bval = 0/0  4-state value = 0
  bit[37]  aval/bval = 0/0  4-state value = 0
  bit[38]  aval/bval = 0/0  4-state value = 0
  bit[39]  aval/bval = 1/1  4-state value = x
L23 "read_vecval_test.v": $finish at simulation time 2
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.7 secs to compile + 0.0 secs to link + 0.2 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Nov 26, 1998  21:40:23