Model {
  Name			  "c5fpid1a"
  Version		  4.00
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowStorageClass	  off
  ExecutionOrder	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Thu Aug 09 00:06:26 2001"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "administrator"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Fri Sep 07 11:56:25 2001"
  ModelVersionFormat	  "1.%<AutoIncrement:2>"
  ConfigurationManager	  "None"
  SimParamPage		  "Solver"
  StartTime		  "0.0"
  StopTime		  "10.0"
  SolverMode		  "Auto"
  Solver		  "ode45"
  RelTol		  "1e-3"
  AbsTol		  "auto"
  Refine		  "1"
  MaxStep		  "auto"
  MinStep		  "auto"
  MaxNumMinSteps	  "-1"
  InitialStep		  "auto"
  FixedStep		  "auto"
  MaxOrder		  5
  OutputOption		  "RefineOutputTimes"
  OutputTimes		  "[]"
  LoadExternalInput	  off
  ExternalInput		  "[t, u]"
  SaveTime		  on
  TimeSaveName		  "tout"
  SaveState		  off
  StateSaveName		  "xout"
  SaveOutput		  on
  OutputSaveName	  "yout"
  LoadInitialState	  off
  InitialState		  "xInitial"
  SaveFinalState	  off
  FinalStateName	  "xFinal"
  SaveFormat		  "Array"
  LimitDataPoints	  on
  MaxDataPoints		  "1000"
  Decimation		  "1"
  AlgebraicLoopMsg	  "warning"
  MinStepSizeMsg	  "warning"
  UnconnectedInputMsg	  "warning"
  UnconnectedOutputMsg	  "warning"
  UnconnectedLineMsg	  "warning"
  InheritedTsInSrcMsg	  "warning"
  SingleTaskRateTransMsg  "none"
  MultiTaskRateTransMsg	  "error"
  IntegerOverflowMsg	  "warning"
  CheckForMatrixSingularity "none"
  UnnecessaryDatatypeConvMsg "none"
  Int32ToFloatConvMsg	  "warning"
  InvalidFcnCallConnMsg	  "error"
  SignalLabelMismatchMsg  "none"
  LinearizationMsg	  "none"
  VectorMatrixConversionMsg "none"
  SfunCompatibilityCheckMsg "none"
  BlockPriorityViolationMsg "warning"
  ArrayBoundsChecking	  "none"
  ConsistencyChecking	  "none"
  ZeroCross		  on
  Profile		  off
  SimulationMode	  "normal"
  RTWSystemTargetFile	  "grt.tlc"
  RTWInlineParameters	  off
  RTWRetainRTWFile	  off
  RTWTemplateMakefile	  "grt_default_tmf"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  TLCProfiler		  off
  TLCDebug		  off
  TLCCoverage		  off
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  OptimizeBlockIOStorage  on
  BufferReuse		  on
  ParameterPooling	  on
  BlockReductionOpt	  on
  RTWExpressionDepthLimit 5
  BooleanDataType	  off
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "c5fpid1a"
    Location		    [480, 85, 851, 248]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "automatic"
    PaperOrientation	    "portrait"
    PaperPositionMode	    "auto"
    PaperType		    "a4letter"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Inport
      Name		      "In1"
      Position		      [15, 58, 45, 72]
      Port		      "1"
      LatchInput	      off
      Interpolate	      on
    }
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem"
      Ports		      [1, 1]
      Position		      [155, 30, 195, 90]
      ShowPortLabels	      on
      TreatAsAtomicUnit	      off
      RTWSystemCode	      "Auto"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      System {
	Name			"Subsystem"
	Location		[470, 62, 845, 255]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"automatic"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 78, 55, 92]
	  Port			  "1"
	  LatchInput		  off
	  Interpolate		  on
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain"
	  Position		  [95, 70, 125, 100]
	  Gain			  "Kp"
	  Multiplication	  "Element-wise(K.*u)"
	  SaturateOnIntegerOverflow on
	}
	Block {
	  BlockType		  TransferFcn
	  Name			  "Integral"
	  Position		  [165, 62, 225, 98]
	  Numerator		  "[1]"
	  Denominator		  "[Ti 0]"
	  AbsoluteTolerance	  "auto"
	  Realization		  "auto"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum"
	  Ports			  [3, 1]
	  Position		  [270, 70, 290, 90]
	  ShowName		  off
	  IconShape		  "round"
	  Inputs		  "+++"
	  SaturateOnIntegerOverflow on
	}
	Block {
	  BlockType		  TransferFcn
	  Name			  "Transfer Fcn"
	  Position		  [165, 127, 225, 163]
	  Numerator		  "[Td 0]"
	  Denominator		  "[Td/N 1]"
	  AbsoluteTolerance	  "auto"
	  Realization		  "auto"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [320, 73, 350, 87]
	  Port			  "1"
	  OutputWhenDisabled	  "held"
	  InitialOutput		  "[]"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Gain"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Gain"
	  SrcPort		  1
	  Points		  [0, 0; 10, 0]
	  Branch {
	    Points		    [0, -5]
	    Branch {
	      Points		      [0, -55; 140, 0]
	      DstBlock		      "Sum"
	      DstPort		      1
	    }
	    Branch {
	      Points		      [10, 0]
	      DstBlock		      "Integral"
	      DstPort		      1
	    }
	  }
	  Branch {
	    Points		    [0, 60]
	    DstBlock		    "Transfer Fcn"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Integral"
	  SrcPort		  1
	  DstBlock		  "Sum"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Transfer Fcn"
	  SrcPort		  1
	  Points		  [50, 0]
	  DstBlock		  "Sum"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Sum"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Outport
      Name		      "Out1"
      Position		      [310, 53, 340, 67]
      Port		      "1"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Line {
      SrcBlock		      "Subsystem"
      SrcPort		      1
      DstBlock		      "Out1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "In1"
      SrcPort		      1
      Points		      [45, 0; 0, -5]
      DstBlock		      "Subsystem"
      DstPort		      1
    }
  }
}