{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 13 17:10:06 2006 " "Info: Processing started: Tue Jun 13 17:10:06 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Code_FD -c Code_FD " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Code_FD -c Code_FD" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse_count.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pulse_count.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_count " "Info: Found entity 1: pulse_count" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Code_FD.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Code_FD.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Code_FD " "Info: Found entity 1: Code_FD" {  } { { "Code_FD.bdf" "" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Code_FD " "Info: Elaborating entity \"Code_FD\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulse_count pulse_count:inst2 " "Info: Elaborating entity \"pulse_count\" for hierarchy \"pulse_count:inst2\"" {  } { { "Code_FD.bdf" "inst2" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 8 200 424 104 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 pulse_count.v(10) " "Warning (10230): Verilog HDL assignment warning at pulse_count.v(10): truncated value with size 32 to match size of target (16)" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 pulse_count.v(12) " "Warning (10230): Verilog HDL assignment warning at pulse_count.v(12): truncated value with size 32 to match size of target (16)" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 16 pulse_count.v(15) " "Warning (10230): Verilog HDL assignment warning at pulse_count.v(15): truncated value with size 24 to match size of target (16)" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "F4.v 1 1 " "Warning: Using design file F4.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 F4 " "Info: Found entity 1: F4" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "F4 " "Warning: Found the following files while searching for definition of entity \"F4\", but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "F4.bdf " "Warning: File: F4.bdf" {  } {  } 0 0 "File: %1!s!" 0 0}  } {  } 0 0 "Found the following files while searching for definition of entity \"%1!s!\", but did not use these files because already using a different file containing the entity definition" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "F4 F4:inst1 " "Info: Elaborating entity \"F4\" for hierarchy \"F4:inst1\"" {  } { { "Code_FD.bdf" "inst1" { Schematic "D:/altera/fpga+dsp/Code_FD/Code_FD.bdf" { { 8 56 176 136 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "INA F4.v(33) " "Info (10035): Verilog HDL or VHDL information at F4.v(33): object \"INA\" declared but not used" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 33 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "CLR F4.v(34) " "Info (10035): Verilog HDL or VHDL information at F4.v(34): object \"CLR\" declared but not used" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 34 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "INB F4.v(35) " "Info (10035): Verilog HDL or VHDL information at F4.v(35): object \"INB\" declared but not used" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 35 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "CLK F4.v(36) " "Info (10035): Verilog HDL or VHDL information at F4.v(36): object \"CLK\" declared but not used" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 36 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "F4_CLK F4.v(37) " "Info (10035): Verilog HDL or VHDL information at F4.v(37): object \"F4_CLK\" declared but not used" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 37 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ENADD F4.v(38) " "Info (10035): Verilog HDL or VHDL information at F4.v(38): object \"ENADD\" declared but not used" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 38 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "F4_CLK F4.v(37) " "Warning (10034): Output port \"F4_CLK\" at F4.v(37) has no driver" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 37 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "ENADD F4.v(38) " "Warning (10034): Output port \"ENADD\" at F4.v(38) has no driver" {  } { { "F4.v" "" { Text "D:/altera/fpga+dsp/Code_FD/F4.v" 38 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[14\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[14\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[14\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[14\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[13\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[13\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[13\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[13\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[12\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[12\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[12\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[12\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "pulse_count:inst2\|PULSE_COUNT\[11\] " "Warning: No clock transition on \"pulse_count:inst2\|PULSE_COUNT\[11\]\" register due to stuck clock or clock enable" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "pulse_count:inst2\|PULSE_COUNT\[11\] clock GND " "Warning: Reduced register \"pulse_count:inst2\|PULSE_COUNT\[11\]\" with stuck clock port to stuck value GND" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/Code_FD/pulse_count.v" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}