{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "F4:F4\|inst26 " "Warning: Node \"F4:F4\|inst26\" is a latch" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 176 800 864 224 "inst26" "" } } } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CE " "Info: Assuming node \"CE\" is an undefined clock" {  } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 8 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CE" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "F4:F4\|inst " "Info: Detected ripple clock \"F4:F4\|inst\" as buffer" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 80 264 328 160 "inst" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4:F4\|inst" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "F4:F4\|inst4 " "Info: Detected ripple clock \"F4:F4\|inst4\" as buffer" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 208 264 328 288 "inst4" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4:F4\|inst4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "F4:F4\|inst5 " "Info: Detected ripple clock \"F4:F4\|inst5\" as buffer" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 80 384 448 160 "inst5" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4:F4\|inst5" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "F4:F4\|inst6 " "Info: Detected ripple clock \"F4:F4\|inst6\" as buffer" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 208 392 456 288 "inst6" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4:F4\|inst6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "F4:F4\|inst1 " "Info: Detected gated clock \"F4:F4\|inst1\" as buffer" {  } { { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { -8 824 888 40 "inst1" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4:F4\|inst1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}