{ "Info" "ITDB_FULL_TCO_RESULT" "CE PC_OUT\[4\] LATCH1:LATCH1\|REG_TEMP\[4\] 7.778 ns register " "Info: tco from clock \"CE\" to destination pin \"PC_OUT\[4\]\" through register \"LATCH1:LATCH1\|REG_TEMP\[4\]\" is 7.778 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CE source 2.825 ns + Longest register " "Info: + Longest clock path from clock \"CE\" to source register is 2.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CE 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CE } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns CE~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'CE~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.139 ns" { CE CE~clkctrl } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.825 ns LATCH1:LATCH1\|REG_TEMP\[4\] 3 REG LCFF_X1_Y8_N1 1 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.825 ns; Loc. = LCFF_X1_Y8_N1; Fanout = 1; REG Node = 'LATCH1:LATCH1\|REG_TEMP\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.556 ns" { CE~clkctrl LATCH1:LATCH1|REG_TEMP[4] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.796 ns ( 63.58 % ) " "Info: Total cell delay = 1.796 ns ( 63.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.42 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "2.825 ns" { CE CE~clkctrl LATCH1:LATCH1|REG_TEMP[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.825 ns" { CE CE~combout CE~clkctrl LATCH1:LATCH1|REG_TEMP[4] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.649 ns + Longest register pin " "Info: + Longest register to pin delay is 4.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LATCH1:LATCH1\|REG_TEMP\[4\] 1 REG LCFF_X1_Y8_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N1; Fanout = 1; REG Node = 'LATCH1:LATCH1\|REG_TEMP\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { LATCH1:LATCH1|REG_TEMP[4] } "NODE_NAME" } "" } } { "LATCH1.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/LATCH1.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(3.096 ns) 4.649 ns PC_OUT\[4\] 2 PIN PIN_43 0 " "Info: 2: + IC(1.553 ns) + CELL(3.096 ns) = 4.649 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'PC_OUT\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "4.649 ns" { LATCH1:LATCH1|REG_TEMP[4] PC_OUT[4] } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 66.59 % ) " "Info: Total cell delay = 3.096 ns ( 66.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 33.41 % ) " "Info: Total interconnect delay = 1.553 ns ( 33.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "4.649 ns" { LATCH1:LATCH1|REG_TEMP[4] PC_OUT[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.649 ns" { LATCH1:LATCH1|REG_TEMP[4] PC_OUT[4] } { 0.000ns 1.553ns } { 0.000ns 3.096ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "2.825 ns" { CE CE~clkctrl LATCH1:LATCH1|REG_TEMP[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.825 ns" { CE CE~combout CE~clkctrl LATCH1:LATCH1|REG_TEMP[4] } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "4.649 ns" { LATCH1:LATCH1|REG_TEMP[4] PC_OUT[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.649 ns" { LATCH1:LATCH1|REG_TEMP[4] PC_OUT[4] } { 0.000ns 1.553ns } { 0.000ns 3.096ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CE PC_OUT\[10\] 5.560 ns Longest " "Info: Longest tpd from source pin \"CE\" to destination pin \"PC_OUT\[10\]\" is 5.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CE 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'CE'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CE } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(3.135 ns) 5.560 ns PC_OUT\[10\] 2 PIN PIN_45 0 " "Info: 2: + IC(1.295 ns) + CELL(3.135 ns) = 5.560 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'PC_OUT\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "4.430 ns" { CE PC_OUT[10] } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.265 ns ( 76.71 % ) " "Info: Total cell delay = 4.265 ns ( 76.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.295 ns ( 23.29 % ) " "Info: Total interconnect delay = 1.295 ns ( 23.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "5.560 ns" { CE PC_OUT[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.560 ns" { CE CE~combout PC_OUT[10] } { 0.000ns 0.000ns 1.295ns } { 0.000ns 1.130ns 3.135ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\] CLR CLK 3.759 ns register " "Info: th for register \"PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\]\" (data pin = \"CLR\", clock pin = \"CLK\") is 3.759 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.522 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 6.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLK } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns CLK~clkctrl 2 COMB CLKCTRL_G1 4 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.970 ns) 3.110 ns F4:F4\|inst6 3 REG LCFF_X1_Y9_N7 3 " "Info: 3: + IC(0.871 ns) + CELL(0.970 ns) = 3.110 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 3; REG Node = 'F4:F4\|inst6'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.841 ns" { CLK~clkctrl F4:F4|inst6 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { 208 392 456 288 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.651 ns) 4.228 ns F4:F4\|inst1 4 COMB LCCOMB_X1_Y9_N20 1 " "Info: 4: + IC(0.467 ns) + CELL(0.651 ns) = 4.228 ns; Loc. = LCCOMB_X1_Y9_N20; Fanout = 1; COMB Node = 'F4:F4\|inst1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.118 ns" { F4:F4|inst6 F4:F4|inst1 } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { -8 824 888 40 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.000 ns) 4.966 ns F4:F4\|inst1~clkctrl 5 COMB CLKCTRL_G0 16 " "Info: 5: + IC(0.738 ns) + CELL(0.000 ns) = 4.966 ns; Loc. = CLKCTRL_G0; Fanout = 16; COMB Node = 'F4:F4\|inst1~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "0.738 ns" { F4:F4|inst1 F4:F4|inst1~clkctrl } "NODE_NAME" } "" } } { "F4.bdf" "" { Schematic "D:/altera/fpga+dsp/CFB_SP/F4.bdf" { { -8 824 888 40 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 6.522 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\] 6 REG LCFF_X2_Y8_N1 3 " "Info: 6: + IC(0.890 ns) + CELL(0.666 ns) = 6.522 ns; Loc. = LCFF_X2_Y8_N1; Fanout = 3; REG Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.556 ns" { F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.417 ns ( 52.39 % ) " "Info: Total cell delay = 3.417 ns ( 52.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.105 ns ( 47.61 % ) " "Info: Total interconnect delay = 3.105 ns ( 47.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "6.522 ns" { CLK CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.522 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } { 0.000ns 0.000ns 0.139ns 0.871ns 0.467ns 0.738ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.651ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.069 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLR 1 PIN PIN_27 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_27; Fanout = 33; PIN Node = 'CLR'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "" { CLR } "NODE_NAME" } "" } } { "CFB_SP.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/CFB_SP.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.660 ns) 3.069 ns PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\] 2 REG LCFF_X2_Y8_N1 3 " "Info: 2: + IC(1.279 ns) + CELL(0.660 ns) = 3.069 ns; Loc. = LCFF_X2_Y8_N1; Fanout = 3; REG Node = 'PULSE_COUNT:PULSE_COUNT\|PULSE_COUNT\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "1.939 ns" { CLR PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/CFB_SP/pulse_count.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.790 ns ( 58.33 % ) " "Info: Total cell delay = 1.790 ns ( 58.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.279 ns ( 41.67 % ) " "Info: Total interconnect delay = 1.279 ns ( 41.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "3.069 ns" { CLR PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.069 ns" { CLR CLR~combout PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } { 0.000ns 0.000ns 1.279ns } { 0.000ns 1.130ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "CFB_SP" "UNKNOWN" "V1" "D:/altera/fpga+dsp/CFB_SP/db/CFB_SP.quartus_db" { Floorplan "D:/altera/fpga+dsp/CFB_SP/" "" "6.522 ns" { CLK CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.522 ns" { CLK CLK~combout CLK~clkctrl F4:F4|inst6 F4:F4|inst1 F4:F4|inst1~clkctrl PULSE_COUNT:PULSE_COUNT|PULSE_COUNT[0] } { 0.000ns 0.000ns 0.139ns 0.871ns 0.467ns 0.738ns 0.890ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.651ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/q