;*********************************************************************;*;*	Hifn Software;*	Licensed Material - Property of Hifn;*  (C) Copyright Hifn Inc. 2005;*	(C) Copyright International Business Machines Corp. 1999;*	All Rights Reserved.;*;*	U.S. Government	Users Restricted Rights - Use, duplication or;*	disclosure restricted by GSA ADP Schedule Contract with;*  Hifn Inc.;*;*********************************************************************;***********************************************************************;       Network Processor Sample Layer-2 Forwarding Code               ;;**********************************************************************;;; File Name; *********; l2.asm;; Purpose; *******; This is a standalone piece of code that demonstrates static Layer-2; forwarding by the Network Processor. It is purely for educational; purposes and has not been optimized for performance.;; This file contains sections to setup the network; processor and dispatch handlers for UP/DN Guided Cells and ; UP/DN unicast frame processing. The file is designed to run in a; wrap mode without a switch fabric so that the UP side is wrapped; to the DN side. The GCH code handles guided traffic from; the control point. The GCH handlers in this sample file include; support for reading/writing locations in memory and returning results; back to the control point. The static layer-2 UP and DN direct tables; (DTs) can be built by sending guided traffic to this sample code. The; guided traffic would contain commands to write these tables to the ; control memory. Sample UP and DN direct tables are included at the; end of this file. The UP unicast dispatch handler parses the; destination MAC address of the frame that is received on one of the; 40 ports. It performs a tree search of the UP DT using the DA MAC as; a key and either discards the frame or enqueues the frame using; values retrieved from the UP DT. The DN unicast dispatch handler; uses the lookup identifier in the frame header to search the DN DT.; It uses the result of the search to enqueue the frame to the; appropriate target port. ;; Document Reference; ******************; Network Processor Assembler Language Programmer's Guide and;   Instruction Summary;; Main Entry Point; ****************; Not Applicable;; Interrupt Handler Entry Points; ******************************; (1)  Timers (0-3)         at 0x0600; (2)  Interrupts (0-3)     at 0x0620; (3)  Rsvd                 at 0x0640; (4)  DN abort             at 0x0660; (5)  DN GTH               at 0x0680; (6)  UP wrap guided       at 0x06A0; (7)  UP wrap data         at 0x06C0; (8)  GPQ                  at 0x06E0; (8)  UP GCH               at 0x0400; (9)  DN GCH               at 0x0800; (10) UP ports 0 thru 39   at 0x1000; (11) DN unicast           at 0x1800; (12) DN multicast         at 0x1C00;; List of Procedures; ******************; None;; Modification History; ********************; Date      By       Change Description         Reason For Change; ****      **       ******************         *****************; 12/02/99  glc,mcb  file created               n/a; 05/26/00  cv, kmw  file updated               Support 4GS3;;**********************************************************************;@INCLUDE "key4tse.inc"@INCLUDE "l2.inc";**********************************************************************;;                     Boot;**********************************************************************;;; Purpose; *******; The boot will :;       1) Configure the Network Processor memories;       2) Configure the Free queue extended stack max size;       3) Init the DRAM controller;       4) Configure the Switch Data Mover's Stack threshold;       5) Configure the Target port data store map;       6) Configure the Port Dispatch table;       7) Set the Target Blade;       8) Configure the ethertype used for Guided traffic;       9) Configure the thresholds for the Buffer control block and ;           the Free Queue extended stack for congestion control; ; Input Parameters; ****************; None;; Returned Values; ***************; None;; General Purpose Registers Destroyed; ***********************************; None;; Array Register Locations Destroyed; **********************************; None;; Pre-Conditions; **************; None;; Post-Conditions; ***************; None;;**********************************************************************;NP_Boot EQU $        cabarb     #cabrequest          ;; Arbitrate for the CAB        ;**************************************************************        ; Configure the NP Memories        ;**************************************************************        ldr        r8, #0x0000        ldr        r9, #0x03F7    ; All Memories        str        cabdata, w8        ldr        r0,#Mem_Cnfg_Reg_Hi_Addr	        ldr        r1,#Mem_Cnfg_Reg_Lo_Addr	        cabaccess  w0, #cabwrite        nop        WAIT       COP_CAB 	        ;**************************************************************        ;  DRAM Controller Initialization        ;     Start the internal h/w initialization by setting        ;     the dram init & island init bits in the init register        ;**************************************************************        ldru       w8, #0x0400         ; DRAM init- r8 = 0x0400, r9 = 0        str        cabdata , w8        ldr        r0,#Init_Reg_Hi_Addr        ldr        r1,#Init_Reg_Lo_Addr        cabaccess  w0, #cabwrite        ;**************************************************************        ;  Poll init done register till both DRAM bits are set to        ;  '1' indicating the DRAM init completion.        ;**************************************************************poll_init_done_again1 EQU $        ldr        r0, #Init_Done_Reg_Hi_Addr        ldr        r1, #Init_Done_Reg_Lo_Addr        cabaccess  w0, #cabread        ldr        w2, cabdata        ldr        r3, #DDS_CM_Init_Done_Mask        and        r2, r3       ; Check only the relevant bits.        cmp        r2, r3       ; Check DRAMs        be         initb        b          poll_init_done_again1        ;**************************************************************        ; Turn on the SIF and Island inits, wait on the DMU's        ;**************************************************************initb   EQU $        ldru       w8, #0x0C00       ; r8 = 0x0C00, r9 = 0        str        cabdata , w8        ldr        r0,#Init_Reg_Hi_Addr        ldr        r1,#Init_Reg_Lo_Addr        cabaccess  w0, #cabwrite                ;**************************************************************        ;  DMU Config and Init        ;     Configure the DMU's before starting initialization on DMU's        ;     Program all the Phy DMU CONFIG registers        ;**************************************************************        ldr        r0, #DMU_Cnfg_Reg_Hi_Addr ; all dmu cnfg regs hi addr        ;**************************************************************        ; Init DMU A        ; Tx Thresh = 2, 10/100 SMII , Tx enable all, Rx enable all,FDX all        ;**************************************************************        ldr        r1, #DMU_A_Cnfg_Reg_Lo_Addr  ; DMU cfg A word 0 not written                                                                                                                                   ldr        r8, #0x0043                  ; Reset value        ldr        r9, #0x07FF        str        cabdata, w8                                                        add        r1, #1                       ; DMU cfg A word 1                                                        cabaccess  w0, #cabwrite                                                      nop                                                                           WAIT       COP_CAB                                          ldr        r8, #0x3FFF        ldr        r9, #0xFC00        str        cabdata, w8        add        r1, #1                       ; DMU cfg A word 2        cabaccess  w0, #cabwrite        nop        WAIT       COP_CAB        ldrh       w8, #0x00        str        cabdata, w8                                     add        r1, #1                       ; DMU cfg A word 3        cabaccess  w0, #cabwrite                                                      nop                                                                           WAIT       COP_CAB        ;**************************************************************        ; Init DMU B        ; Tx Thresh = 2, 10/100 SMII , Tx enable all, Rx enable all, FDX all        ;**************************************************************        ldr        r1, #DMU_B_Cnfg_Reg_Lo_Addr  ; DMU cfg B word 0 not written               ldr        r8, #0x0043                  ; Reset value        ldr        r9, #0x07FF        str        cabdata, w8                                                     add        r1,#1                        ; DMU cfg B word 1                                                           cabaccess  w0, #cabwrite                                                   nop                                                                        WAIT       COP_CAB         ldr        r8, #0x3FFF        ldr        r9, #0xFC00        str        cabdata, w8        add        r1, #1                       ; DMU cfg B word 2        cabaccess  w0, #cabwrite        nop        WAIT       COP_CAB        ldrh       w8, #0x00        str        cabdata, w8                                     add        r1, #1                       ; DMU cfg B word 3        cabaccess  w0, #cabwrite                                                      nop                                                                           WAIT       COP_CAB        ;**************************************************************        ; Init DMU C        ; Tx Thresh = 2, 10/100 SMII , Tx enable all, Rx enable all, FDX all        ;**************************************************************        ldr        r1, #DMU_C_Cnfg_Reg_Lo_Addr  ; Word 0 not written                                    ldr        r8, #0x0043                  ; Reset value        ldr        r9, #0x07FF        str        cabdata, w8                                                      add        r1,#1                        ; DMU cfg C word 1                                                           cabaccess  w0, #cabwrite                                                    nop                                                                         WAIT       COP_CAB        ldr        r8, #0x3FFF        ldr        r9, #0xFC00        str        cabdata, w8        add        r1, #1                       ; DMU cfg C word 2        cabaccess  w0, #cabwrite        nop        WAIT       COP_CAB        ldrh       w8, #0x00        str        cabdata, w8                                     add        r1, #1                       ; DMU cfg C word 3        cabaccess  w0, #cabwrite                                                      nop                                                                           WAIT       COP_CAB        ;**************************************************************        ; Init DMU D