?? l2.asm
字號(hào):
; Tx Thresh = 2, 10/100 SMII , Tx enable all, Rx enable all, FDX all ;************************************************************** ldr r1, #DMU_D_Cnfg_Reg_Lo_Addr ; Word 0 not written ldr r8, #0x0043 ; Reset value ldr r9, #0x07FF str cabdata, w8 add r1,#1 ; DMU cfg D word 1 cabaccess w0, #cabwrite nop WAIT COP_CAB ldr r8, #0x3FFF ldr r9, #0xFC00 str cabdata, w8 add r1, #1 ; DMU cfg D word 2 cabaccess w0, #cabwrite nop WAIT COP_CAB ldrh w8, #0x00 str cabdata, w8 add r1, #1 ; DMU cfg C word 3 cabaccess w0, #cabwrite nop WAIT COP_CAB ;************************************************************** ; DMU's should be configured ; Poll DMU reset bit to wait for all enables ;************************************************************** ldr r0, #DMU_Cnfg_Reg_Hi_Addr ; all dmu cnfg regs hi addrdmu_a ldr r1, #DMU_A_Cnfg_Reg_Lo_Addr cabaccess w0, #cabread ldr w2,cabdata ldr r3, #0x8000 and r2, r3 ;; Mask off all but high bit cmp r2, #0x0000 ;; Make sure reset is off bne dmu_admu_b ldr r1, #DMU_B_Cnfg_Reg_Lo_Addr cabaccess w0, #cabread ldr w2,cabdata ldr r3, #0x8000 and r2, r3 ;; Mask off all but high bit cmp r2, #0x0000 ;; Make sure reset is off bne dmu_bdmu_c ldr r1, #DMU_C_Cnfg_Reg_Lo_Addr cabaccess w0, #cabread ldr w2,cabdata ldr r3, #0x8000 and r2, r3 ;; Mask off all but high bit cmp r2, #0x0000 ;; Make sure reset is off bne dmu_cdmu_d ldr r1, #DMU_D_Cnfg_Reg_Lo_Addr cabaccess w0, #cabread ldr w2,cabdata ldr r3, #0x8000 and r2, r3 ;; Mask off all but high bit cmp r2, #0x0000 ;; Make sure reset is off bne dmu_d ;************************************************************** ; Start the dmu h/w initialization by setting ; the DMU init bit in the init register ; rather than reading and or'ing the SIF and Island Bits back in ; I'm just setting them again ;************************************************************** ldru w8, #0xFC00 ; r8 = 0xFC00, r9 = 0 str cabdata , w8 ldr r0, #Init_Reg_Hi_Addr ldr r1, #Init_Reg_Lo_Addr cabaccess w0, #cabwrite ;************************************************************** ; Poll init done register till all the bits are set to ; '1' indicating the island initialization completion. ;**************************************************************poll_init_done_again2 EQU $ ldr r0, #Init_Done_Reg_Hi_Addr ldr r1, #Init_Done_Reg_Lo_Addr cabaccess w0, #cabread ldr w2,cabdata ldr r3, #0xFFFF and r2, r3 ; Check only the relevant bits. cmp r2, r3 be TP_data_store_map b poll_init_done_again2 ;************************************************************** ; Set up Target Port Data Store Map(TP_DS_MAP) Register ; DMU C & D = DS1 ; DMC A & B = DS0 ;**************************************************************TP_data_store_map EQU $ ldr r0, #Tp_DS_Map_Reg_Hi_Addr ; same hi addr for all writes ldr r8, #0xAAAA ldr r9, #0xAAAA str cabdata, w8 ldr r1, #Tp_DS_Map_Reg_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ldr r8, #0xAA55 ldr r9, #0x5555 str cabdata, w8 add r1,#1 ; move to next word cabaccess w0, #cabwrite nop WAIT COP_CAB ldru w8, #0x5555 ; r8 = 0x5555, r9 = 0 str cabdata, w8 add r1,#1 ; move to next word cabaccess w0, #cabwrite nop WAIT COP_CAB ldru w8, #0x5000 ; r8 = 0x5000, r9 = 0 str cabdata, w8 ldr r0, #Up_TP_DSU_Reg_Hi_Addr ldr r1, #Up_TP_DSU_Reg_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ;************************************************************** ; Set up dispatcher start points ;************************************************************** ;************************************************************** ; Setup the Port Dispatch ; These are the entry points for Data Traffic when not using HW ; classifier ; port config for 40 inbound port - code entry 0x1000h ; r3 and r0 are set up here and used throughout the dispatcher cfg ;************************************************************** ldr r2, #dispatch_port0_cfg_lo_addr ; init to port 0 ldr r3, #0x0003 ; addr offset, we need to access the 4th ; word of each entry in the cfg table ; all entries are being written at 4th word ldr r8, #0x0004 ; 21-6 = Code entry point ldr r9, #0x0020 ; 3-2 start fish,1-0 = number of fish str cabdata, w8 ldr r0, #dispatch_cfg_hi_addr dispinit EQU $ ldr r1, r2 ; start with port 0 sll r1, #4 ; shift the port number over 4 bits or r1, r3 ; or in other word selects cabaccess w0, #cabwrite add r2, #1 ; inc to next port cmp r2, #0x0028 ; compare to port 40 bne dispinit ; not equal repeat ;************************************************************** ; Dn Unicast Frame Dispatch code entry 0x1800 ;************************************************************** ldr r1, #dispatch_DN_F_UC_lo_addr ; Address the Dn enet Ucframe (pct=48), LSW of Fish ; or r1, r3 ; or in other word selects ldr r8, #0x0006 ; Code_entry = 0x1800h, HWA disabled, ldr r9, #0x0022 ; CU Label Gen disabled ==> Need ENQUP NOLABEL str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; Dn Multicast Frame Dispatch code entry 0x1c00 ;************************************************************** ldr r1, #dispatch_DN_F_MC_lo_addr ; Address the Dn enet Mcframe (pct=49), LSW of Fish or r1, r3 ; or in other word selects ldr r8, #0x0007 ; Code_entry = 0x1C00h, HWA disabled, ldr r9, #0x0022 ; CU Label Gen disabled ==> Need ENQUP NOLABEL str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; For up GCH, entry point of 0x0400h ;************************************************************** ldr r1, #dispatch_UP_GCH_lo_addr ; Address the UP GCH port, LSW of Fish or r1, r3 ; or in other word selects ldr r8, #0x0001 ; Code_entry = 0x0400h, LabelGen enabled, ldr r9, #0x0020 ; CU Label Gen enabled str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; UP Wrap Guided entry = 0x6a0 ;************************************************************** ldr r1, #dispatch_UP_Wrap_G_lo_addr ; Address the UP Wrap Guided port (43 = 31x), LSW of Fish or r1, r3 ; or in other word selects ldr r8, #0x0001 ; Code_entry = 0x06a0h, HWA disabled,LabelGen enabled ldr r9, #0xA800 ; CU Label Gen disabled ==> Need ENQUP NOLABEL str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; Dn GCH entry = 0x800 ;************************************************************** ldr r1, #dispatch_DN_GCH_lo_addr ; Address the DN Guided port(pct=46), LSW of Fish or r1, r3 ; or in other word selects ldr r8, #0x0002 ; Code_entry = 0x0800h, HWA disabled, ldr r9, #0x0022 ; CU Label Gen disabled ==> Need ENQDN NOLABEL str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; Wrap Data Port entry = 0x6c0 ;************************************************************** ldr r1, #dispatch_UP_Wrap_D_lo_addr or r1, r3 ; or in other word selects ldr r8, #0x0001 ldr r9, #0xB000 str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; Dn Abort Port entry = 0x660 ; port 54 and 55 ;************************************************************** ldr r1, #dispatch_Dn_Abort_lo_addr or r1, r3 ; or in other word selects ldr r8, #0x0001 ldr r9, #0x9800 str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB add r1, #0x10 ; increment to port 55 str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; Dn GTH Entry = 0x680 ;************************************************************** ldr r1, #dispatch_Dn_GTH_lo_addr or r1, r3 ; or in other word selects ldr r8, #0x0001 ldr r9, #0xA000 str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; GPQ Entry = 0x6E0 ;************************************************************** ldr r1, #dispatch_GPQ_lo_addr or r1, r3 ; or in other word selects ldr r8, #0x0001 ; Code_entry = 0x6E0h, ldr r9, #0xB800 ; str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; Set All Interrupts Entry to 620 ; loop through all four interrupt levels?? 快捷鍵說(shuō)明
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