?? l2.asm
字號(hào):
;************************************************************** ldr r1, #dispatch_Int0_lo_addr or r1, r3 ; or in other word selects ldr r8, #0x0001 ; Code_entry = 0x620h, ldr r9, #0x8800 intrset EQU $ str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB add r1, #0x0010 ; Increment to next address cmp r1, #0x03C3 ; compare to port address 244003C3 bne intrset ; not equal repeat ; Address the timers ;************************************************************** ; Set All Timer Entry to 600 ; loop through all four timer levels ;************************************************************** ldr r8, #0x0001 ; Code_entry = 0x600h, ldr r9, #0x8000 ldr r1,#dispatch_Timer0_lo_addr or r1, r3 ; or in other word selectstimerset EQU $ str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB add r1, #0x0010 ; Increment to next address cmp r1, #0x0403 ; compare to port address 24400403 bne timerset ; not equal repeat ;************************************************************** ; Set Reserved Entry = 0x640 ; loop from port 50 to 53, 41 and 44 ;************************************************************** ldr r1, #dispatch_Res50_lo_addr or r1, r3 ; or in other word selects ldr r8, #0x0001 ; Code_entry = 0x640h, ldr r9, #0x9000 ; reserv_set EQU $ str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB add r1, #0x0010 ; Increment to next address cmp r1, #0x0363 ; compare to port address 24400363 bne reserv_set ; not equal repeat ldr r1, #dispatch_Res41_lo_addr or r1, r3 ; or in other word selects str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ldr r1, #dispatch_Res44_lo_addr or r1, r3 ; or in other word selects str cabdata, w8 cabaccess w0, #cabwrite nop wait COP_CAB ;************************************************************** ; Set up Port Control Blocks Cut-Through threshold ; Start address is 0x10010000 and the threshold is in word 4 ;************************************************************** ldrh w8, #0x00 ; Set threshold to 1 buffers str cabdata, w8 ldr r0,#up_pcb_ctrl_block_hi_addr ldr r1,#up_pcb_ctrl_block_lo_addr + 4pcbinit EQU $ cabaccess w0, #cabwrite add r1, #0x0010 ; inc to next port cmp r1, #up_pcb_ctrl_block_end_addr + 4 ; compare to port 39 ble pcbinit ; less than or equal repeat ;************************************************************** ; Write the MY_TB register and Local Target Blade ;************************************************************** ldr r8, #0x0000 ldr r9, #0x0008 ; TB = TB0, r8 = 0x8000, r9 = 0 str cabdata, w8 ldr r0, #My_Target_Blade_Hi_Addr ldr r1, #My_Target_Blade_Lo_Addr cabaccess w0, #cabwrite ldr r0, #Local_TB_Vec_Reg_Hi_Addr ; local TB Vector ldr r1, #Local_TB_Vec_Reg_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ;************************************************************** ; Set E_Type to C100 for Guided Traffic ;************************************************************** ldru w8, #0xC100 ; r8 = 0xC100, r9 = 0 str cabdata, w8 ldr r0, #E_Type_C_Reg_Hi_Addr ldr r1, #E_Type_C_Reg_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ;************************************************************** ; Set Up Buffer control Block (BCB) Thresholds ; These are the thresholds used by the Enqueue Dequeue Sched ; in order to determine when to discard packets ;************************************************************** ldru w8, #0x3800 ; Set BCB_Th_GC = 7- r8 = 0x3800, r9 = 0 str cabdata, w8 ldr r0, #BCB_FQ_Threshold_Hi_Addr ldr r1, #BCB_FQ_Threshold_GC_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ldru w8, #0x0400 ; 64 Buffers perform a partial packet discard str cabdata, w8 ; cabdata = 0x0400 0000 ldr r1, #BCB_FQ_Threshold_0_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ldru w8, #0x0800 ; 128 buffers perform packet discard str cabdata, w8 ; cabdata = 0x0800 0000 ldr r1, #BCB_FQ_Threshold_1_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ldru w8, #0x1000 ; 256 buffers perform media flow ctrl str cabdata, w8 ; cabdata = 0x1000 0000 ldr r1, #BCB_FQ_Threshold_2_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ;************************************************************** ; Set Up Dn FQ_ES Thresholds ; These are the thresholds used by the Enqueue Dequeue Sched ; in order to determine when to discard packets ;************************************************************** ldrh w8, #0x00 ; Set FQ_ES_Th0 = 64 twins str cabdata, w8 ldr r0, #FQ_ES_TH_Hi_Addr ldr r1, #FQ_ES_TH0_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ldru w8, #0x0010 ; Set FQ_ES_Th1 = 128 twins str cabdata, w8 ; cabdata = 0x0010 0000 ldr r1, #FQ_ES_TH1_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ldru w8, #0x0020 ; Set FQ_ES_Th2 = 256 twins str cabdata, w8 ; cabdata = 0x0020 0000 ldr r1, #FQ_ES_TH2_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ;************************************************************** ; Enable CLPs ;************************************************************** ; Write the Enable CLP register ldru w8, #0xff80 ; Enable all CLPs str cabdata, w8 ; cabdata = 0xFF80 0000 ldr r0, #CLP_Enable_Reg_Hi_Addr ldr r1, #CLP_Enable_Reg_Lo_Addr cabaccess w0, #cabwrite nop WAIT COP_CAB ;************************************************************** ; Reset Interrupt Vectors All ; Class 0,1,2,3, Interrupts ;************************************************************** ldr r0, #Int_Mask_Hi_Addr ; Interrupt vector address ldr r1, #Int_Vector_0_Lo_Addr cabaccess w0, #cabread nop WAIT COP_CAB ldr r1, #Int_Vector_1_Lo_Addr cabaccess w0, #cabread nop WAIT COP_CAB ldr r1, #Int_Vector_2_Lo_Addr cabaccess w0, #cabread nop WAIT COP_CAB ldr r1, #Int_Vector_3_Lo_Addr cabaccess w0, #cabreadConfigure_Interrupts EQU $ ;************************************************************** ; Configure the interrupts to be processed ;************************************************************** ;************************************************************** ; Set which GxH gets dispatched for interrupts ;************************************************************** ldru w8, #0xE000 ; intr handled by any GxH str cabdata , w8 ; cabdata = 0xE000 0000 ldr r0, #Int_Target_Reg_Hi_Addr ldr r1, #Int_Target_Reg0_Lo_Addr cabaccess w0, #cabwrite ; write interrupt target Vector 0 str cabdata , w8 ldr r1, #Int_Target_Reg1_Lo_Addr cabaccess w0, #cabwrite ; write interrupt target Vector 1 str cabdata , w8 ldr r1, #Int_Target_Reg2_Lo_Addr cabaccess w0, #cabwrite ; write interrupt target Vector 2 str cabdata , w8 ldr r1, #Int_Target_Reg3_Lo_Addr cabaccess w0, #cabwrite ; write interrupt target Vector 3 ;************************************************************** ; Enable all interrupt sources ;************************************************************** ldruo w8, #0xFFFF str cabdata , w8 ; cabdata = 0xFFFF FFFF ldr r0, #Int_Mask_Hi_Addr ldr r1, #Int_Mask_0_Lo_Addr cabaccess w0, #cabwrite ; write interrupt 0 mask (all on) str cabdata , w8 ldr r1, #Int_Mask_1_Lo_Addr cabaccess w0, #cabwrite ; write interrupt 1 mask (all on) str cabdata , w8 ldr r1, #Int_Mask_2_Lo_Addr cabaccess w0, #cabwrite ; write interrupt 2 mask (all on) str cabdata , w8 ldr r1, #Int_Mask_3_Lo_Addr cabaccess w0, #cabwrite ; write interrupt 3 mask (all on) ;************************************************************** ; Set which GxH can process timer interrupts ;************************************************************** ldru w8, #0x8000 ; counters processed by GCH only str cabdata , w8 ; cabdata = 0x8000 0000 ldr r0, #Timer_Target_Reg_Hi_Addr ; Write hi addr once ldr r1, #Timer_Target_Reg0_Lo_Addr cabaccess w0, #cabwrite ; write counter target Vector 0 str cabdata , w8 ldr r1, #Timer_Target_Reg1_Lo_Addr cabaccess w0, #cabwrite ; write counter target Vector 1 str cabdata , w8 ldr r1, #Timer_Target_Reg2_Lo_Addr cabaccess w0, #cabwrite ; write counter target Vector 2 str cabdata , w8 ldr r1, #Timer_Target_Reg3_Lo_Addr cabaccess w0, #cabwrite ; write counter target Vector 3?? 快捷鍵說(shuō)明
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