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?? l2.asm

?? 基于IBM的NPU
?? ASM
?? 第 1 頁 / 共 5 頁
字號:
        ;**************************************************************        ; Set the NP_ready register indicating NP is        ; ready to receive external frames.        ;**************************************************************NPReady    EQU $        ldru       w8, #0x8000        str        cabdata , w8        ldr        r0, #NP_Rdy_Hi_Addr        ldr        r1, #NP_Rdy_Lo_Addr        cabaccess  w0, #cabwrite        cabarb     #cabrelease        ;**************************************************************        ; Init Control Memory location with cnt=0 for dispatch handler log        ;**************************************************************                ldr    r6      ,#Unexpected_disp_Log_hi_addr  ; Read Interrupt cnt from CM - D0-d        ldr    r7      ,#Unexpected_disp_Log_Lo_addr        str    LCBA0   , w6              ; Store the address into LeafControlBlockAddr        ldrh   w0     , #0x00        str    TSR0[0] , w0              ; Clear the dispatch count and         str    TSR0[4] , w0              ; dispatch type        mwr    #0x0000                   ; Write to control memory                ;**************************************************************        ; Exit        ;**************************************************************        exit;**********************************************************************;;                     Misc Dispatch Handlers                           ;;**********************************************************************;;; Purpose; *******; This code handles the following dispatches: Timers(0-3),; Interrupts(0-3), Reserved, DN Multicast, DN abort, DN GTH, UP wrap; guided, and UP wrap data. ; ; The miscellaneous dispatch handlers have separate entry points but ; share code that stores away the dispatch type in control memory.;; These dispatches are unexpected during the execution of this sample; forwarding code. The handlers are in place for this example to log; unexpected dispatches.   ;; Input Parameters; ****************; None;; Returned Values; ***************; None;; General Purpose Registers Destroyed; ***********************************; wo : dispatch count; w4 : dispatch type;; Array Register Locations Destroyed; **********************************; None;; Pre-Conditions; **************; None;; Post-Conditions; ***************; None;;**********************************************************************;        ;**************************************************************;        ;                     Timers (0-3)                             ;        ;**************************************************************;        ; Start at location 0x0600       ORG 0x0600        ldr        r5, #0x0600        b          dispatch_log        ;**************************************************************;        ;                     Interrupts (0-3)                         ;        ;**************************************************************;        ; Start at location 0x0620       ORG 0x0620        ldr        r5, #0x0620        b          dispatch_log        ;**************************************************************;        ;                     DN Abort                                 ;        ;**************************************************************;        ; Start at location 0x0660             ORG 0x0660        ldr        r5, #0x0660        b          dispatch_log        ;**************************************************************;        ;                     DN GTH                                   ;        ;**************************************************************;        ; Start at location 0x0680             ORG 0x0680        ldr        r5, #0x0680        b          dispatch_log                ;**************************************************************;        ;                     UP Wrap Guided                           ;        ;**************************************************************;        ; Start at location 0x06A0       ORG 0x06A0        ldr        r5, #0x06A0        b          dispatch_logGuided_Wrap EQU $        ldr        r5, #0x06A1        b          dispatch_log        ;**************************************************************;        ;                     UP Wrap Data                             ;        ;**************************************************************;        ; Start at location 0x06C0       ORG 0x06C0        ldr        r5, #0x06C0        b          dispatch_log        ;**************************************************************;        ; Common unexpected dispatch code snippet        ;**************************************************************; dispatch_log EQU $                                  ldr    r0, #Unexpected_disp_Log_hi_addr ; Store the address of              ldr    r1, #Unexpected_disp_Log_lo_addr ; dispatch log into            str    LCBA0   , w0         ; Leaf Control Block Address 0                        mrd    #0x0000              ; Do a mem read tree search cmd                                        ; results in TSR0            ldr    w0     , TSR0[0]     ; get disp count from ctrl mem             add    r1     , #1          ; inc disp count            str    TSR0[0] , w0         ; Store the new count into TSR            str    TSR0[4] , w4         ; Store the disp type into TSR            mwr    #0x0000              ; Write type and cnt to ctrl mem                           exit            ;**********************************************************************;;            UP Guided Cell Handler                                    ;;**********************************************************************;;; Purpose; *******; This code handles guided traffic on the UP side. It supports read and; write commands. CAB or control memories can be read or written. Place; holders exist in the code to handle other types of commands. It does; not support the duplicate write command - all writes are treated as block; writes. Also, this sample code does not look at the resp/-req,; ack/-noack, early/-late, neg/-all, up/-down, or the gth,-gch bits in; the frame control. It assumed that all guided frames have the following; settings:;   req/-resp = 0 (request);   ack/-noack = 1 (return acknowledgement to CP);   early/-late = 0 (acknowledge *after* guided frame processing);   neg/-all = 0 (acknowledge *all* guided frames);   up/-down = 1 (guided frame processed on *up* side);   gth/-gch = 0 (*gch* picoprocessor);; Guided frames consist of 1 word of ; frame control followed by 1 word of correlator followed by; the guided commands. The read and write guided commands consist of ; a 1 word command, a 1 word address, 1 word of element parameters and; the element data. For this sample guided cell handler, the frame must; fit into 4 fish (64 bytes) and contain only 1 command.;; The Ethernet MAC examines the Ethernet type of all frames to; distinguish guided traffic from data traffic. When a frame arrives; with an ETYPE that matches the value in the E_Type_C register (C100; in this example), the MAC strips off 14 bits (DA, SA, EType) and; stores the guided frame data in the U_DS memory.  ;  ; Input Parameters; ****************; When the guided cell handler is dispatched, 4 fish have been read from; the UP data store to the DataPool.;; Returned Values; ***************; None;; General Purpose Registers Destroyed; ***********************************; r0  : running pointer to DataPool; r2  : element increment; w4  : starting address; w6  : running address; r8  : element size; r9  : element count; w10 : working register; r12 : count of words in element; w14 : working register;; Array Register Locations Destroyed; **********************************; None;; Pre-Conditions; **************; None;; Post-Conditions; ***************; None;;**********************************************************************;       ORG 0x0400                       ; Start at location 0x0400Guided        EQU $       cabarb #cabrequest               ; Request the CAB       ldr    r0 , #My_Target_Blade_Hi_Addr       ldr    r1 , #My_Target_Blade_Lo_Addr       cabaccess  w0, #cabread          ; Request CAB Read at My_TB Reg       wait   COP_CAB                   ; Wait for the CAB processor to complete       cabarb #cabrelease               ; Releases the CAB access              ldr    w4 , cabdata              ; Save  My_TB in GPR W4       ldr    w14, DataPool[0x00]       ; Read the Frame Control info       cmp    r15, r5                   ; Compare TB in frame to my blade       bne    Remote_Blade              ; Jump if frame not for current blade              ldr    w2 , DataPool[0x08]       ; Load the Control information       ldr    r1 , #gf_rw_mask          ; Look at GC type bits to see if cmd is       and    r1 , r3                   ; a read/write or one of the others       cmp    r1 , #gf_rw               ; Is it a read/write       bne    Not_Read_Write            ;   no, jump to handle all other cmds       ;***************************************************************************       ; Reads/Writes       ;***************************************************************************              cabarb #cabrequest               ; Request the CAB              ldr    w4 , DataPool[0x0C]       ; Load Starting Address from DataPool       ldr    w8 , DataPool[0x10]       ; Load Count Parameters from DataPool:                                        ;   Element Increment, Element Size, Element Count       ldr    r2 , r8                   ; Copy Element Increment in R2...       slr    r2 , #8                   ; ...and align it on LSB       ldr    r0 , #0x00FF              ;       and    r8 , r0                   ; Leave only Element Size in R8       ldr    r0 , #0x14                ; Preset DataPool Word Ptr to 1st word positionElementLoop   EQU $       ldr    w6 , w4                   ; Preset Running Address to Starting Address       ldr    r12, r8                   ; Preset "Word Count in Element" to Element SizeWordLoop      EQU $                     ; Determine if it is read or write       ldr    r1 , #gf_read_mask        ;        and    r1 , r3                   ;       cmp    r1 , #gf_read_mask        ; If read bit is set,       be     Guided_read               ;   jump to handle read                             ;****************************************************************       ;   Writes       ;****************************************************************       ldr    r10, r4                   ; Check island for which the guided       and    r10, #gf_isl_id_mask      ; write is intended. If ctrl mem,       cmp    r10, #gf_ctrl_mem_id      ; do a  memory write transfer.       bne    do_cab_write       ;****************************************************************       ; Control Memory write       ;****************************************************************                                               ; w6 has the address       ldr    r15, #0x000F

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