pRsrc[unit]->pciFunc,
                              PCI_CFG_BASE_ADDRESS_0, 
			      pRsrc[unit]->iobaseCsr |
                              PCI_BASE_IO);
		 
            pciConfigOutLong (pRsrc[unit]->pciBus, 
			      pRsrc[unit]->pciDevice, 
			      pRsrc[unit]->pciFunc,
                              PCI_CFG_BASE_ADDRESS_1, 
			      pRsrc[unit]->membaseCsr);

            pciConfigOutByte (pRsrc[unit]->pciBus, 
			      pRsrc[unit]->pciDevice, 
			      pRsrc[unit]->pciFunc,
                              PCI_CFG_DEV_INT_LINE, 
			      pRsrc[unit]->irq);
            }
	    
        /*
         * get memory base address and IO base address
         * Note: we read it in again, even if we just wrote it out because  
         * the device can change what we wrote
         */

        pciConfigInLong (pRsrc[unit]->pciBus, 
			 pRsrc[unit]->pciDevice, 
			 pRsrc[unit]->pciFunc,
	                 PCI_CFG_BASE_ADDRESS_0, &iobaseCsr);

        pciConfigInLong (pRsrc[unit]->pciBus, 
			 pRsrc[unit]->pciDevice, 
			 pRsrc[unit]->pciFunc,
                         PCI_CFG_BASE_ADDRESS_1, &membaseCsr);

        pciConfigInByte (pRsrc[unit]->pciBus, 
			 pRsrc[unit]->pciDevice, 
			 pRsrc[unit]->pciFunc,
                         PCI_CFG_DEV_INT_LINE, &irq);

        /*
         * mask off registers. IO base needs to be masked off because bit0
         * will always be set to 1
         */

        membaseCsr   &= PCI_MEMBASE_MASK;
        iobaseCsr    &= PCI_IOBASE_MASK;

#ifdef INCLUDE_MMU_BASIC
	    if (sysMmuMapAdd ((void *)(membaseCsr & PCI_DEV_MMU_MSK),
			      PCI_DEV_ADRS_SIZE,
			      VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
			      VM_STATE_MASK_CACHEABLE,
			      VM_STATE_VALID      | VM_STATE_WRITABLE |
			      VM_STATE_CACHEABLE_NOT
			      ) == ERROR)
			{
		 	/* for now, exit, but later break and stop where we're at 
		    				when we're detecting multiple units */
		 	return (ERROR);

			}
#else
#warning INCLUDE_MMU_BASIC not defined
#endif /* INCLUDE_MMU_BASIC */

		/* over write the resource table with values read */

		pRsrc[unit]->membaseCsr   = membaseCsr;
		pRsrc[unit]->iobaseCsr    = iobaseCsr;
		pRsrc[unit]->irq          = irq;
        pRsrc[unit]->irqvec       = irq + EXT_INTERRUPT_BASE;

		/* enable mapped memory and IO addresses */

        pciConfigOutWord (	pRsrc[unit]->pciBus, 
			  				pRsrc[unit]->pciDevice, 
			  				pRsrc[unit]->pciFunc,
                          	PCI_CFG_COMMAND, PCI_CMD_IO_ENABLE |
                          	PCI_CMD_MEM_ENABLE | PCI_CMD_MASTER_ENABLE);

        /* disable sleep mode */

        pciConfigOutWord (pRsrc[unit]->pciBus, 
			  pRsrc[unit]->pciDevice, 
			  pRsrc[unit]->pciFunc, 
			  PCI_CFG_MODE, 
                          SLEEP_MODE_DIS);
        }

    return NULL; 
    }

/*******************************************************************************
*
* sysRtl81x9IntEnable - enable interrupts
*
* This routine enables interrupts.  This may involve operations on
* interrupt control hardware.
*
* RETURNS: OK or ERROR for invalid arguments.
*/

STATUS sysRtl81x9IntEnable
    (
    int	level		/* level number */
    )
    {
    return (sysIntEnablePIC(level));
    }

/*******************************************************************************
*
* sysLanIntDisable - disable interrupts
*
* This routine disables interrupts.  This may involve operations on
* interrupt control hardware.
*
* RETURNS: OK or ERROR for invalid arguments.
*/

STATUS sysRtl81x9IntDisable
    (
    int	level		/* level number */
    )
    {
    return (sysIntDisablePIC(level));
    }


/******************************************************************************
*
* sysRtl81x9EndLoad - load an istance of the rtl81x9 END driver
*
* This routine loads the rtl81x9 driver with the parameters specified by
* the resource table for the device, and some default values.
*
* The END device load string formed by this routine is in the following
* following format.
* <devMemAddr>:<devIoAddr>:<pciMemBase>:<vecnum>:<intLvl>:<memAdrs>
* :<memSize>:<memWidth>:<flags>:<buffMultiplier>
*
* .IP <devMemAddr>
* Device register base memory address
* .IP <devIoAddr>
* Device register base IO address
* .IP <pciMemBase>
* Base address of PCI memory space
* .IP <vecNum>
* Interrupt vector number.
* .IP <intLvl>
* Interrupt level.
* .IP <memAdrs>
* Memory pool address or NONE.
* .IP <memSize>
* Memory pool size or zero.
* .IP <memWidth>
* Memory system size, 1, 2, or 4 bytes (optional).
* .IP <flags>
* Device specific flags.
* .IP <buffMultiplier>
* Buffer Multiplier or NONE. If NONE is specified, it defaults to 2
*
* This routine only loads and initializes instance zero of the device.
* If the user wishes to use more than one rtl81x9 devices, this routine
* should be changed.
*
* RETURNS: pointer to END object or ERROR.
*
* SEE ALSO: rtl81x9EndLoad()
*/
 
END_OBJ * sysRtl81x9EndLoad
    (
    char * pParamStr,   /* ptr to initialization parameter string */
    void * unused       /* unused optional argument */
    )
    {
    /*
     * The rtl81x9 driver END_LOAD_STRING should be:
     * <devMemAddr>:<devIoAddr>:<pciMemBase>:<vecnum>:<intLvl>:<memAdrs>
     * :<memSize>:<memWidth>:<flags>:<buffMultiplier>
     * Note that unit string is prepended by the mux, so we
     * don't put it here.
     */

    int unit_number;
	char * pStr = NULL;
    char paramStr [200];
    static char rtl81x9ParamTemplate [] = 
			"0x%x:0x%x:0x%x:%d:%d:-1:-1:-1:0x%x:%d:0x%x";
    END_OBJ * pEnd;



    if (strlen (pParamStr) == 0)
        {
       /*
        * muxDevLoad() calls us twice.  If the string is
        * zero length, then this is the first time through
        * this routine.
        */
 
        pEnd = (END_OBJ *) rtl81x9EndLoad (pParamStr);
        }
    else
        {
       /*
        * On the second pass through here, we actually create
        * the initialization parameter string on the fly.
        * Note that we will be handed our unit number on the
        * second pass and we need to preserve that information.
        * So we use the unit number handed from the input string.
        */

		/* Work out the Unit Number to initialise */

    	unit_number = atoi (pParamStr);
		if ((unit_number < 0) || (unit_number > NELEMENTS (rtl81x9Brds)))
			{
			return NULL;
			}
		else
			{
        	pStr = strcpy (paramStr, pParamStr);
 
        	/* Now, we get to the end of the string */
 
	        pStr += strlen (paramStr);
	 
	        /* finish off the initialization parameter string */
			sprintf (pStr, rtl81x9ParamTemplate,
	                     /* device memory IO base */
	                     (UINT) pRsrc[unit_number]->membaseCsr + CPU_PCI_MEM_ADRS,
	                     /* device Io base */
                     	(UINT) pRsrc[unit_number]->iobaseCsr  + CPU_PCI_IO_ADRS,
                     	PCI2DRAM_BASE_ADRS,					/* pciMemBase */
                     	pRsrc[unit_number]->irqvec,       	/* interrupt IRQ vector */
                     	pRsrc[unit_number]->irq,          	/* interrupt irq number */
                     	0,                         			/* ?????? */
                     	0,                         			/* offset */
                     	RTL81X9_END_FLAGS          			/* flags */
                     	);
 
        	if ((pEnd = (END_OBJ *) rtl81x9EndLoad (paramStr)) == (END_OBJ *)ERROR)
            	{
            	logMsg ("Error: rtl81x9EndLoad failed to load driver\n",
		    					0, 0, 0, 0, 0, 0);
            	}
        	}
		}
 
    return (pEnd);
    }
#endif /* INCLUDE_RTL_81X9_END */