?? gfd_addr.s
字號:
;====================================================================
; File Name : gfdaddr.a
; Function : GFD Define Address Register (Assembly)
; Program : Shin, On Pil (SOP)
; Date : Sep 06, 2003
; Version : 0.0
; History
; 0.0 : Programming start (February 18,2002) -> SOP by Willhua
;
;====================================================================
; GBLL FPGA
;FPGA SETL {TRUE}
; [FPGA
INTC_BASE EQU 0x40000000
PMU_BASE EQU 0x40001000
RTC_BASE EQU 0x40002000
GPT_BASE EQU 0x40003000
UART0_BASE EQU 0X40004000
UART1_BASE EQU 0X40005000
SPI_BASE EQU 0X40006000
IIC_BASE EQU 0x40007000
AC97_BASE EQU 0x40008000
MMC_BASE EQU 0x40009000
PORT_BASE EQU 0x4000b000
DMAC_BASE EQU 0x41001000
LCDC_BASE EQU 0x41002000
MMA_BASE EQU 0x41003000
; |
;INTC_BASE EQU 0x10000000
;PMU_BASE EQU 0x10001000
;RTC_BASE EQU 0x10002000
;GPT_BASE EQU 0x10003000
;UART0_BASE EQU 0X10004000
;UART1_BASE EQU 0X10005000
;SPI_BASE EQU 0X10006000
;IIC_BASE EQU 0x10007000
;AC97_BASE EQU 0x10008000
;MMC_BASE EQU 0x10009000
;PORT_BASE EQU 0x1000b000
;DMAC_BASE EQU 0x11001000
;LCDC_BASE EQU 0x11002000
;MMA_BASE EQU 0x11003000
; ]
INTC_IEN EQU (INTC_BASE+0X00)
INTC_IMSK EQU (INTC_BASE+0X80)
INTC_IFCE EQU (INTC_BASE+0X10)
INTC_IRSTAT EQU (INTC_BASE+0X18)
INTC_ISTAT EQU (INTC_BASE+0X20)
INTC_IMSTAT EQU (INTC_BASE+0X28)
INTC_IFSTAT EQU (INTC_BASE+0X30)
INTC_FEN EQU (INTC_BASE+0XC0)
INTC_FMSK EQU (INTC_BASE+0XC4)
INTC_FFCE EQU (INTC_BASE+0XC8)
INTC_FRSTAT EQU (INTC_BASE+0XCC)
INTC_FSTAT EQU (INTC_BASE+0XD0)
INTC_FFSTAT EQU (INTC_BASE+0XD4)
INTC_PLV EQU (INTC_BASE+0XD8)
RTC_YMD EQU (RTC_BASE+0X00) ;//year ,month ,day regment
RTC_HMS EQU (RTC_BASE+0X04) ;//hour ,minute ,second regment
RTC_ALRM EQU (RTC_BASE+0X08) ;//alarm time regment
RTC_CTRL EQU (RTC_BASE+0X0c) ;//rtc control regment
RTC_IEN EQU (RTC_BASE+0X10) ;//interrupt enable regment
RTC_ISTAT EQU (RTC_BASE+0X14) ;//interrupt status regment
RTC_SAMP EQU (RTC_BASE+0X18) ;//sample regment
RTC_WCNT EQU (RTC_BASE+0X1c) ;//watchdog count regment
RTC_WSVCE EQU (RTC_BASE+0X20) ;//Watchdog service regment
GPT1_CNTL EQU (GPT_BASE+0x00)
GPT1_SCAL EQU (GPT_BASE+0x04)
GPT1_COMP EQU (GPT_BASE+0x08)
GPT1_CAPT EQU (GPT_BASE+0x0c)
GPT1_CNT EQU (GPT_BASE+0x10)
GPT1_STAT EQU (GPT_BASE+0x14)
GPT2_CNTL EQU (GPT_BASE+0x18)
GPT2_SCAL EQU (GPT_BASE+0x1c)
GPT2_COMP EQU (GPT_BASE+0x20)
GPT2_CAPT EQU (GPT_BASE+0x24)
GPT2_CNT EQU (GPT_BASE+0x28)
GPT2_STAT EQU (GPT_BASE+0x2c)
;//PWM
PWM1_CNTL EQU (GPT_BASE+0X30)
PWM1_P EQU (GPT_BASE+0X34)
PWM1_S EQU (GPT_BASE+0X38)
PWM1_C EQU (GPT_BASE+0X3C)
PWM1_CNT EQU (GPT_BASE+0X40)
PWM1_STAT EQU (GPT_BASE+0X44)
PWM2_CNTL EQU (GPT_BASE+0X48)
PWM2_S EQU (GPT_BASE+0X4C)
PWM2_P EQU (GPT_BASE+0X50)
PWM2_C EQU (GPT_BASE+0X54)
PWM2_CNT EQU (GPT_BASE+0X58)
PWM2_STAT EQU (GPT_BASE+0X5C)
UART0_THR EQU (UART0_BASE+0X00)
UART0_RBR EQU (UART0_BASE+0X00)
UART0_DLL EQU (UART0_BASE+0X00)
UART0_DLH EQU (UART0_BASE+0X04)
UART0_IER EQU (UART0_BASE+0X04)
UART0_IIR EQU (UART0_BASE+0X08)
UART0_FCR EQU (UART0_BASE+0X08)
UART0_LCR EQU (UART0_BASE+0X0c)
UART0_MCR EQU (UART0_BASE+0X10)
UART0_LSR EQU (UART0_BASE+0X14)
UART0_MSR EQU (UART0_BASE+0X18)
;//UART2
UART1_THR EQU (UART1_BASE+0X00)
UART1_RBR EQU (UART1_BASE+0X00)
UART1_DLL EQU (UART1_BASE+0X00)
UART1_DLH EQU (UART1_BASE+0X04)
UART1_IER EQU (UART1_BASE+0X04)
UART1_IIR EQU (UART1_BASE+0X08)
UART1_FCR EQU (UART1_BASE+0X08)
UART1_LCR EQU (UART1_BASE+0X0c)
UART1_MCR EQU (UART1_BASE+0X10)
UART1_LSR EQU (UART1_BASE+0X14)
UART1_MSR EQU (UART1_BASE+0X18)
;//SPI
SPICR EQU (SPI_BASE+0X00)
SPIBR EQU (SPI_BASE+0X04)
SPISR EQU (SPI_BASE+0X08)
SPITR EQU (SPI_BASE+0X0C)
SPIRR EQU (SPI_BASE+0x10)
;//IIC
;//AC97
;//MMC
;//GPIO
;//EMI
EMI_SRAM_REGBASE EQU 0x41000000 ; //Sdram sram register base;
EMI_NAND_REGBASE EQU 0x11000000 ; //NAND FLASH register base;
EMI_SMCONF EQU (EMI_SRAM_REGBASE+0x00) ;//adress of sram time_sequence register
EMI_CSAB EQU (EMI_SRAM_REGBASE+0x04) ; //adress of CSA and CSB chip select register
EMI_CSCD EQU (EMI_SRAM_REGBASE+0X08) ;//adress of CSC and CSD chip select register
EMI_CSEF EQU (EMI_SRAM_REGBASE+0X0c) ; //adress of CSE and CSF chip select register
EMI_REMAP EQU (EMI_SRAM_REGBASE+0X10) ;//Remap register select boot memory
EMI_SDCFG1 EQU (EMI_SRAM_REGBASE+0X14) ;//sram and adram time_sequence register I
EMI_SDCFG2 EQU (EMI_SRAM_REGBASE+0X18) ;//sram and adram time_sequence register II
;
EMI_NADDR EQU (EMI_NAND_REGBASE+0X00) ;//adress of Nand Flash adress register
EMI_NCOM EQU (EMI_NAND_REGBASE+0X04) ;//adress of Nand Flash control register
EMI_NSTATUS EQU (EMI_NAND_REGBASE+0X0c) ;//adress of Nand Flash status register
EMI_NERRORADDR1 EQU (EMI_NAND_REGBASE+0X10) ;//adress of Nand Flash error register I
EMI_NERRORADDR2 EQU (EMI_NAND_REGBASE+0X14) ;//adress of Nand Flash error register II
EMI_NCONF EQU (EMI_NAND_REGBASE+0X18) ;//adress of Nand Flash config register
EMI_NINTR EQU (EMI_NAND_REGBASE+0X1c) ;//Int clear
EMI_NFINECC EQU (EMI_NAND_REGBASE+0X20) ; //ECC complish
EMI_NIDLE EQU (EMI_NAND_REGBASE+0X24) ; //Compish register
EMI_NDATA EQU (0x11000200)
;//DMAC
DMA_ISTAT EQU (DMAC_BASE+0x20) ;//Read
DMA_ITCSTAT EQU (DMAC_BASE+0x50) ;//Read
DMA_ITCCLR EQU (DMAC_BASE+0x60) ;//Write
DMA_RITCSTAT EQU (DMAC_BASE+0x70) ;//Read
DMA_IERRSTAT EQU (DMAC_BASE+0x80) ;//Read
DMA_IERRCLR EQU (DMAC_BASE+0x90) ;//Write
DMA_RIERRSTAT EQU (DMAC_BASE+0xa0) ;//Read
DMA_ENCH EQU (DMAC_BASE+0xB0) ;//Read; Indicate which channel can be used;
ADDR_ESS_CONFIGURATION EQU (DMAC_BASE+0xC0)
DMA_C0SA EQU (DMAC_BASE+0x000) ;//DMA channel 0 registers;
DMA_C0DA EQU (DMAC_BASE+0x004) ;
DMA_C0CTL EQU (DMAC_BASE+0x00c) ;
DMA_C0CFG EQU (DMAC_BASE+0x010) ;
DMA_C1SA EQU (DMAC_BASE+0x100) ;//DMA channel 1 registers; R/W
DMA_C1DA EQU (DMAC_BASE+0x104) ;
DMA_C1CTL EQU (DMAC_BASE+0x10c) ;
DMA_C1CFG EQU (DMAC_BASE+0x110) ;
DMA_C2SA EQU (DMAC_BASE+0x200) ;//DMA channel 2 registers; R/W
DMA_C2DA EQU (DMAC_BASE+0x204) ;
DMA_C2CTL EQU (DMAC_BASE+0x20c) ;
DMA_C2CFG EQU (DMAC_BASE+0x210) ;
DMA_C3SA EQU (DMAC_BASE+0x300) ;//DMA channel 3 registers; R/W
DMA_C3DA EQU (DMAC_BASE+0x304) ;
DMA_C3CTL EQU (DMAC_BASE+0x30c) ;
DMA_C3CFG EQU (DMAC_BASE+0x310) ;
DMA_C4SA EQU (DMAC_BASE+0x400) ;//DMA channel 4 registers; R/W
DMA_C4DA EQU (DMAC_BASE+0x404) ;
DMA_C4CTL EQU (DMAC_BASE+0x40c) ;
DMA_C4CFG EQU (DMAC_BASE+0x410) ;
DMA_C5SA EQU (DMAC_BASE+0x500) ;//DMA channel 5 registers; R/W
DMA_C5DA EQU (DMAC_BASE+0x504) ;
DMA_C5CTL EQU (DMAC_BASE+0x50c) ;
DMA_C5CFG EQU (DMAC_BASE+0x510)
;//LCDC
LCD_VS_BASE EQU 0x81000000 ;WHICH IS ASSUMED BECAUSE OF UN-ALLOCARTION
LCD_SSA EQU (LCDC_BASE+0x00) ;Screen Start Address Register
LCD_SIZE EQU (LCDC_BASE+0x04) ;Size Register
LCD_PCR EQU (LCDC_BASE+0x08) ;Panel Configuration Register
LCD_HCR EQU (LCDC_BASE+0x0c) ;Horizontal Configuration Register
LCD_VCR EQU (LCDC_BASE+0x10) ;Vertical Configuration Register
LCD_PWMR EQU (LCDC_BASE+0x14) ;PWM Contrast Control Register
LCD_LECR EQU (LCDC_BASE+0x18) ;LCD Gray Palette Mapping Register
LCD_DMACR EQU (LCDC_BASE+0x1c) ;DMA Control Register
LCD_LCDICR EQU (LCDC_BASE+0x20) ;Interrupt Configuration Register
LCD_LCDISR EQU (LCDC_BASE+0x24) ;Interrupt Status Register
CDC_LGPMR EQU (LCDC_BASE+0x40) ;The begin of address of grey_reg
;//MMA
;// ISR
pISR_RESET EQU (ISR_BADDR+0x0)
pISR_UNDEF EQU (ISR_BADDR+0x4)
pISR_SWI EQU (ISR_BADDR+0x8)
pISR_PABORT EQU (ISR_BADDR+0xc)
pISR_DABORT EQU (ISR_BADDR+0x10)
pISR_RESERVED EQU (ISR_BADDR+0x14)
pISR_IRQ EQU (ISR_BADDR+0x18)
pISR_FIQ EQU (ISR_BADDR+0x1c)
pISR_RTC EQU (ISR_BADDR+0x20)
pISR_DMA EQU (ISR_BADDR+0x24)
pISR_EMI EQU (ISR_BADDR+0x28)
pISR_GPT EQU (ISR_BADDR+0x2c)
pISR_USB EQU (ISR_BADDR+0x30)
pISR_SPI EQU (ISR_BADDR+0x34)
pISR_MMC EQU (ISR_BADDR+0x38)
pISR_UART1 EQU (ISR_BADDR+0x3c)
pISR_UART0 EQU (ISR_BADDR+0x40)
pISR_I2C EQU (ISR_BADDR+0x44)
pISR_AC97 EQU (ISR_BADDR+0x48)
pISR_MMA EQU (ISR_BADDR+0x4c)
pISR_EXT17 EQU (ISR_BADDR+0x50)
pISR_EXT16 EQU (ISR_BADDR+0x54)
pISR_EXT15 EQU (ISR_BADDR+0x58)
pISR_EXT0 EQU (ISR_BADDR+0x5c)
pISR_EXT1 EQU (ISR_BADDR+0x60)
pISR_EXT2 EQU (ISR_BADDR+0x64)
pISR_EXT3 EQU (ISR_BADDR+0x68)
pISR_EXT4 EQU (ISR_BADDR+0x6c)
pISR_EXT5 EQU (ISR_BADDR+0x70)
pISR_EXT6 EQU (ISR_BADDR+0x74)
pISR_EXT7 EQU (ISR_BADDR+0x78)
pISR_EXT8 EQU (ISR_BADDR+0x7c)
pISR_EXT9 EQU (ISR_BADDR+0x80)
pISR_EXT10 EQU (ISR_BADDR+0x84)
pISR_EXT11 EQU (ISR_BADDR+0x88)
pISR_EXT12 EQU (ISR_BADDR+0x8c)
pISR_EXT13 EQU (ISR_BADDR+0x90)
pISR_EXT14 EQU (ISR_BADDR+0x94)
;//INT NUM
INT_RTC EQU 31
INT_DMA EQU 30
INT_EMI EQU 29
INT_GPT EQU 28
INT_USB EQU 27
INT_SPI EQU 26
INT_MMC EQU 25
INT_UART1 EQU 24
INT_UART0 EQU 23
INT_I2C EQU 22
INT_AC97 EQU 21
INT_MMA EQU 20
INT_EXT17 EQU 19
INT_EXT16 EQU 18
INT_EXT15 EQU 17
INT_NONE1 EQU 16
INT_EXT0 EQU 15
INT_EXT1 EQU 14
INT_EXT2 EQU 13
INT_EXT3 EQU 12
INT_EXT4 EQU 11
INT_EXT5 EQU 10
INT_EXT6 EQU 9
INT_EXT7 EQU 8
INT_EXT8 EQU 7
INT_EXT9 EQU 6
INT_EXT10 EQU 5
INT_EXT11 EQU 4
INT_EXT12 EQU 3
INT_EXT13 EQU 2
INT_EXT14 EQU 1
INT_NONE2 EQU 0
;// PENDING BIT
BIT_RTC EQU (0x1<<31)
BIT_DMA EQU (0x1<<30)
BIT_EMI EQU (0x1<<29)
BIT_GPT EQU (0x1<<28)
BIT_USB EQU (0x1<<27)
BIT_SPI EQU (0x1<<26)
BIT_MMC EQU (0x1<<25)
BIT_UART1 EQU (0x1<<24)
BIT_UART0 EQU (0x1<<23)
BIT_I2C EQU (0x1<<22)
BIT_AC97 EQU (0x1<<21)
BIT_MMA EQU (0x1<<20)
BIT_EXT17 EQU (0x1<<19)
BIT_EXT16 EQU (0x1<<18)
BIT_EXT15 EQU (0x1<<17)
BIT_NONE1 EQU (0x1<<16)
BIT_EXT0 EQU (0x1<<15)
BIT_EXT1 EQU (0x1<<14)
BIT_EXT2 EQU (0x1<<13)
BIT_EXT3 EQU (0x1<<12)
BIT_EXT4 EQU (0x1<<11)
BIT_EXT5 EQU (0x1<<10)
BIT_EXT6 EQU (0x1<<9)
BIT_EXT7 EQU (0x1<<8)
BIT_EXT8 EQU (0x1<<7)
BIT_EXT9 EQU (0x1<<6)
BIT_EXT10 EQU (0x1<<5)
BIT_EXT11 EQU (0x1<<4)
BIT_EXT12 EQU (0x1<<3)
BIT_EXT13 EQU (0x1<<2)
BIT_EXT14 EQU (0x1<<1)
BIT_NONE2 EQU (0x1)
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