?? gfd_addr.h
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/********************************************************************************************
*filename: gfd_addr.c
*author: willhua
*create date: 2003-7-14 14:17
*description: This file defined registers of all the module
*modify history:
*misc:
********************************************************************************************/
#ifndef __GFDADDR_H__
#define __GFDADDR_H__
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************
define INTC registers
***************************************************/
#define BASE_INTC 0x10000000
#define INTC_IEN ( BASE_INTC+0X0 )
#define INTC_IMSK ( BASE_INTC+0X8 )
#define INTC_IFCE ( BASE_INTC+0X10 )
#define INTC_IRSTAT ( BASE_INTC+0X18 )
#define INTC_ISTAT ( BASE_INTC+0X20 )
#define INTC_IMSTAT ( BASE_INTC+0X28 )
#define INTC_IFSTAT ( BASE_INTC+0X30 )
#define INTC_FEN ( BASE_INTC+0XC0 )
#define INTC_FMSK ( BASE_INTC+0XC4 )
#define INTC_FFCE ( BASE_INTC+0XC8 )
#define INTC_FRSTAT ( BASE_INTC+0XCC )
#define INTC_FSTAT ( BASE_INTC+0XD0 )
#define INTC_FFSTAT ( BASE_INTC+0XD4 )
#define INTC_PLV ( BASE_INTC+0XD8 )
/*************************************************
define GPT registers
*************************************************/
#define GPT_BASE 0x10003000
#define GPT1_LCR (GPT_BASE + 0x00)
#define GPT1_CCR (GPT_BASE + 0x04)
#define GPT1_CR (GPT_BASE + 0x08)
#define GPT1_SCR (GPT_BASE + 0x0c)
#define GPT1_MSR (GPT_BASE + 0x10)
/************************************************
define PWM registers
************************************************/
#define PWM1_CNTL (GPT_BASE + 0X30)
#define PWM1_P (GPT_BASE + 0X34)
#define PWM1_S (GPT_BASE + 0X38)
#define PWM1_C (GPT_BASE + 0X3C)
#define PWM1_CNT (GPT_BASE + 0X40)
#define PWM1_STAT (GPT_BASE + 0X44)
#define PWM2_CNTL (GPT_BASE + 0X48)
#define PWM2_S (GPT_BASE + 0X4C)
#define PWM2_P (GPT_BASE + 0X50)
#define PWM2_C (GPT_BASE + 0X54)
#define PWM2_CNT (GPT_BASE + 0X58)
#define PWM2_STAT (GPT_BASE + 0X5C)
/*************************************************
defien RTC registers
*************************************************/
#define RTC_BASE 0x10002000
#define RTC_YMD (RTC_BASE + 0X00) //year ,month ,day regment
#define RTC_HMS (RTC_BASE + 0X04) //hour ,minute ,second regment
#define RTC_ALRM (RTC_BASE + 0X08) //alarm time regment
#define RTC_CTRL (RTC_BASE + 0X0c) //rtc control regment
#define RTC_IEN (RTC_BASE + 0X10) //interrupt enable regment
#define RTC_ISTAT (RTC_BASE + 0X14) //interrupt status regment
#define RTC_SAMP (RTC_BASE + 0X18) //sample regment
#define RTC_WCNT (RTC_BASE + 0X1c) //watchdog count regment
#define RTC_WSVCE (RTC_BASE + 0X20) //Watchdog service regment
/*********************************************
define UART registers
*********************************************/
#define UART1_BASE 0X10004000
#define UART1_THR (UART1_BASE+0X00)
#define UART1_RBR (UART1_BASE+0X00)
#define UART1_DLL (UART1_BASE+0X00)
#define UART1_DLH (UART1_BASE+0X04)
#define UART1_IER (UART1_BASE+0X04)
#define UART1_IIR (UART1_BASE+0X08)
#define UART1_FCR (UART1_BASE+0X08)
#define UART1_LCR (UART1_BASE+0X0c)
#define UART1_MCR (UART1_BASE+0X10)
#define UART1_LSR (UART1_BASE+0X14)
#define UART1_MSR (UART1_BASE+0X18)
#define UART2_BASE 0X10005000
#define UART2_THR (UART2_BASE+0X00)
#define UART2_RBR (UART2_BASE+0X00)
#define UART2_DLL (UART2_BASE+0X00)
#define UART2_DLH (UART2_BASE+0X04)
#define UART2_IER (UART2_BASE+0X04)
#define UART2_IIR (UART2_BASE+0X08)
#define UART2_FCR (UART2_BASE+0X08)
#define UART2_LCR (UART2_BASE+0X0c)
#define UART2_MCR (UART2_BASE+0X10)
#define UART2_LSR (UART2_BASE+0X14)
#define UART2_MSR (UART2_BASE+0X18)
/*************************************
define LCDC registers
*************************************/
#define BASE_LCDC 0x11002000 //;BASE ADDRESS OF LCDC
#define VS_BASE 0x31af0000 //;WHICH IS ASSUMED BECAUSE OF UN-ALLOCARTION
#define SSA (BASE_LCDC+0x00) //;Screen Start Address Register
#define SIZE (BASE_LCDC+0x04) //;Size Register
#define PCR (BASE_LCDC+0x08) //;Panel Configuration Register
#define HCR (BASE_LCDC+0x0c) //;Horizontal Configuration Register
#define VCR (BASE_LCDC+0x10) //;Vertical Configuration Register
#define PWMR (BASE_LCDC+0x14) //;PWM Contrast Control Register
#define LECR (BASE_LCDC+0x18) //;LCD Gray Palette Mapping Register
#define DMACR (BASE_LCDC+0x1c) //;DMA Control Register
#define LCDICR (BASE_LCDC+0x20) //;Interrupt Configuration Register
#define LCDISR (BASE_LCDC+0x24) //;Interrupt Status Register
#define LGPMR (BASE_LCDC+0x40) //;The begin of address of grey_reg
/**************************************
define SPI registers
****************************************/
#define BASE_SPI_1 0X10006000
#define SPICR (BASE_SPI_1 + 0X00)
#define SPIBR (BASE_SPI_1 + 0X04)
#define SPISR (BASE_SPI_1 + 0X08)
#define SPITR (BASE_SPI_1 + 0X0C)
#define SPIRR (BASE_SPI_1 + 0x10)
/************************************** xiaoj 03.11.20
define DMA registers
****************************************/
#define DMACbase 0x11000000
#define DMACIntStatus (DMACbase+0x1020) //Read
#define DMACIntTCStatus (DMACbase+0x1050) //Read
#define DMACIntTCClear (DMACbase+0x1060) //Write
#define DMACRawIntTCStatus (DMACbase+0x1070) //Read
#define DMACIntErrorStatus (DMACbase+0x1080) //Read
#define DMACIntErrClr (DMACbase+0x1090) //Write
#define DMACRawIntErrorStatus (DMACbase+0x10a0) //Read
#define DMACEnbldChns (DMACbase+0x10B0) //Read; Indicate which channel can be used;
#define ADDRESS_CONFIGURATION (DMACbase+0x10C0)
#define DMACC0SrcAddr (DMACbase+0x1000) //DMA channel 0 registers;
#define DMACC0DestAddr (DMACbase+0x1004)
#define DMACC0Control (DMACbase+0x100c)
#define DMACC0Configuration (DMACbase+0x1010)
#define DMACC1SrcAddr (DMACbase+0x1100) //DMA channel 1 registers; R/W
#define DMACC1DestAddr (DMACbase+0x1104)
#define DMACC1Control (DMACbase+0x110c)
#define DMACC1Configuration (DMACbase+0x1110)
#define DMACC2SrcAddr (DMACbase+0x1200) //DMA channel 2 registers; R/W
#define DMACC2DestAddr (DMACbase+0x1204)
#define DMACC2Control (DMACbase+0x120c)
#define DMACC2Configuration (DMACbase+0x1210)
#define DMACC3SrcAddr (DMACbase+0x1300) //DMA channel 3 registers; R/W
#define DMACC3DestAddr (DMACbase+0x1304)
#define DMACC3Control (DMACbase+0x130c)
#define DMACC3Configuration (DMACbase+0x1310)
#define DMACC4SrcAddr (DMACbase+0x1400) //DMA channel 4 registers; R/W
#define DMACC4DestAddr (DMACbase+0x1404)
#define DMACC4Control (DMACbase+0x140c)
#define DMACC4Configuration (DMACbase+0x1410)
#define DMACC5SrcAddr (DMACbase+0x1500) //DMA channel 5 registers; R/W
#define DMACC5DestAddr (DMACbase+0x1504)
#define DMACC5Control (DMACbase+0x150c)
#define DMACC5Configuration (DMACbase+0x1510)
/**************************************
define EMI registers
****************************************/
#define EMI_SRAM_REGBASE 0x11000000 //Sdram sram register base;
#define EMI_NAND_REGBASE 0x11000100 //NAND FLASH register base;
#define EMIADDR_SMCONF ( EMI_SRAM_REGBASE+0x00 ) //adress of sram time_sequence register
#define EMIADDR_CSGBAB ( EMI_SRAM_REGBASE+0x04 ) //adress of CSA and CSB chip select register
#define EMIADDR_CSGBCD ( EMI_SRAM_REGBASE+0X08 ) //adress of CSC and CSD chip select register
#define EMIADDR_CSGBEF ( EMI_SRAM_REGBASE+0Xc ) //adress of CSE and CSF chip select register
#define EMIADDR_REMAP ( EMI_SRAM_REGBASE+0X10 ) //Remap register select boot memory
#define EMIADDR_SDCONF1 ( EMI_SRAM_REGBASE+0X14 ) //sram and adram time_sequence register I
#define EMIADDR_SDCONF2 ( EMI_SRAM_REGBASE+0X18 ) //sram and adram time_sequence register II
#define GFD_NAND_REGBASE 0x11000100 //NAND FLASH register base;
#define GFD_DMA_REGBASE 0x11001000
#define GFD_NAND_ADDR ( GFD_NAND_REGBASE+0X00 ) //adress of Nand Flash adress register
#define GFD_NAND_COM ( GFD_NAND_REGBASE+0X04 ) //adress of Nand Flash control register
#define GFD_NAND_STATUS ( GFD_NAND_REGBASE+0X0c ) //adress of Nand Flash status register
#define GFD_NAND_ERRORADDR1 ( GFD_NAND_REGBASE+0X10 ) //adress of Nand Flash error register I
#define GFD_NAND_ERRORADDR2 (GFD_NAND_REGBASE+0X14 ) //adress of Nand Flash error register II
#define GFD_NAND_CONF ( GFD_NAND_REGBASE+0X18 ) //adress of Nand Flash config register
#define GFD_NAND_INTR (GFD_NAND_REGBASE+0X1c ) //Int clear
#define GFD_NAND_FINECC (GFD_NAND_REGBASE+0X20 ) //ECC complish
#define GFD_NAND_IDLE (GFD_NAND_REGBASE+0X24 ) //Compish register
#define GFD_NAND_DATA (GFD_NAND_REGBASE+0X100 ) //0x11000200
//********************************
//PMU
//*****************************
#define PMU_BASE 0x10001000
#define PMU_PLTR (PMU_BASE+0X00)
#define PMU_PMCR (PMU_BASE+0X04)
#define PMU_PUCR (PMU_BASE+0X08)
#define PMU_PSCR (PMU_BASE+0X0C)//OPEN MODULE
#define PMU_PCDR (PMU_BASE+0X10)
#define PMU_PMDR (PMU_BASE+0X14)
#ifdef __cplusplus
}
#endif
#endif /*__GFDADDR_H__*/
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