/* @(#) pSOSystem/PPC V221 */
/***********************************************************************/
/*                                                                     */
/*   MODULE:  mpc8xx/sdev/fpgacfg.h                                    */
/*   DATE:    2000/2/22                                                */
/*   AUTHOR:  Dong Aiping                                              */
/*   PURPOSE: Define maro of FPGA configuration                        */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*           Copyright 1999 - 2000, ZHONGXING TELECOM CO.,LTD.         */
/*                      ALL RIGHTS RESERVED                            */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*  Notes: 
        If you replant it to another board,the following need changed:
             FPGA_PortReg
             FPGA_PROGRAM
             FPGA_CCLK   
             FPGA_DIN
             FPGA_DONE 
             FPGA_INIT
       another change is a function in fpgacfg.c
            delay_us()                                                 */
/***********************************************************************/
#ifndef _FPGACFG_H
#define _FPGACFG_H

#define FPGA_PortReg  S_PortBDataReg  /* Data Register of input/output port*/

#define FPGA_PROGRAM    0x00020000 /* 14  out */
#define FPGA_CCLK       0x00010000 /* 15  out */
#define FPGA_DIN        0x00008000 /* 16  out */
#define FPGA_DONE       0x00004000 /* 17  inport*/
#define FPGA_INIT       0x00002000 /* 18  inport*/

#define FPGA_SetPin(pins,value) (value)?FPGA_PortReg |=(pins):FPGA_PortReg &= ~(pins)
#define FPGA_GetPin(pins)       ((FPGA_PortReg&(pins)) ? 1 : 0 )
#define FPGA_WriteBit(value)    { FPGA_PortReg &= ~(FPGA_CCLK); \
              ((value)!=0)? FPGA_PortReg|=(FPGA_DIN):FPGA_PortReg&= ~(FPGA_DIN); \
              FPGA_PortReg |= FPGA_CCLK; }

int FPGA_Config(UCHAR *pFpgaData, ULONG DataLen);

#endif  /* _FPGACFG_H */