?? flash32bts.c
字號:
for(ii=0;ii<FLASH_WRITE_LOOP;ii++){
/*Data# polling(DQ7)*/
if((ReadReg((ULONG)start)&0x00800080)==(data&0x00800080))break;
}
if(ii==FLASH_WRITE_LOOP)break;
/*rc=ReadReg((ULONG)start)&0x00380038;
WriteReg((ULONG)start,0x00ff00ff);
if(rc!=0)break;
*/
}
i+=4; start+=4;
if(i>=DataLen)break; else data=0xffffffff;
if((i+4)>DataLen)memmove((UCHAR *)&data,BufAddr+i,DataLen-i);
else data=*(ULONG *)(BufAddr+i);
}
if(i<DataLen) return SDE_FLASH_FAIL;
else
{
start = (UCHAR *)(BaseAddr + Offset);
if(memcmp(start,mas->Base,mas->Size)!=0)return SDE_FLASH_FAIL;
return SDE_OK;
}
}
static int SstFlash32Cntrl(void *pDataBuf, int cmd, void *pParam, int maxlen)
{
Flash32CfgStruct *pCfg=(Flash32CfgStruct *)pDataBuf;
switch(cmd)
{
case SDC_GET_UNIT_SIZE:
if(maxlen!=sizeof(ULONG))return SDE_INVALID_ARG;
*(ULONG *)pParam=pCfg->UnitSize;
return SDE_OK;
case SDC_GET_BASE_ADDR:
if(maxlen!=sizeof(ULONG))return SDE_INVALID_ARG;
*(ULONG *)pParam=pCfg->BaseAddr;
return SDE_OK;
case SDC_GET_MAX_SIZE:
if(maxlen!=sizeof(ULONG))return SDE_INVALID_ARG;
*(ULONG *)pParam=pCfg->MaxSize;
return SDE_OK;
case SDC_WRITE_FLASH:
return write_sstflash(pDataBuf,pParam,maxlen);
case SDC_READ_FLASH:
return read_sstflash(pDataBuf,pParam,maxlen);
case SDC_ERASE_CHIP:
{
ULONG cs;
int ret=SDE_OK;
for(cs=0;cs<8;cs++){
ULONG i;
ULONG BaseAddr=pCfg->CSRange[cs][0]+pCfg->BaseAddr;
if(pCfg->CSRange[cs][1]==0)break;
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00aa00aa);
WriteReg(BaseAddr+(ULONG)(0x2aaa<<2),0x00550055);
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00800080);
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00aa00aa);
WriteReg(BaseAddr+(ULONG)(0x2aaa<<2),0x00550055);
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00100010);
for(i=0;i<FLASH_ERASE_CHIP_LOOP;i++){
if((ReadReg(BaseAddr)&0x00800080)==0x00800080)break;
}
if(i==FLASH_ERASE_CHIP_LOOP)ret=SDE_FLASH_FAIL;
}
return ret;
}
case SDC_ERASE_SECTOR:
{
ULONG offset=*(ULONG *)pParam;
int ret=SDE_OK;
ULONG i;
ULONG BaseAddr=0xFFFFFFFF;
for(i=0;i<8 && pCfg->CSRange[i][1]!=0;i++)
if(pCfg->CSRange[i][0]<=offset &&pCfg->CSRange[i][1]> offset){
BaseAddr=pCfg->CSRange[i][0]+pCfg->BaseAddr;
offset -= pCfg->CSRange[i][0];
}
if(BaseAddr==0xFFFFFFFF)return SDE_INVALID_ARG;
if(maxlen!=sizeof(ULONG))return SDE_INVALID_ARG;
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00aa00aa);
WriteReg(BaseAddr+(ULONG)(0x2aaa<<2),0x00550055);
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00800080);
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00aa00aa);
WriteReg(BaseAddr+(ULONG)(0x2aaa<<2),0x00550055);
WriteReg(BaseAddr+offset,0x00500050);
for(i=0;i<FLASH_ERASE_SECTOR_LOOP;i++){
if((ReadReg(BaseAddr+offset)&0x00800080)==0x00800080)break;
}
if(i==FLASH_ERASE_SECTOR_LOOP)ret=SDE_FLASH_FAIL;
return ret;
}
default:
return SDE_UNKNOW_CMD;
}
/* return SDE_OK; */
}
/****************************************************************************/
/* NOTE: The following are the INTEL TE28F320C3 flash operation functions */
/****************************************************************************/
static int IntelFlash32C3Cntrl(void *pDataBuf, int cmd, void *pParam, int maxlen)
{
Flash32CfgStruct *pCfg=(Flash32CfgStruct *)pDataBuf;
switch(cmd)
{
case SDC_GET_UNIT_SIZE:
if(maxlen!=sizeof(ULONG))return SDE_INVALID_ARG;
*(ULONG *)pParam=pCfg->UnitSize;
return SDE_OK;
case SDC_GET_BASE_ADDR:
if(maxlen!=sizeof(ULONG))return SDE_INVALID_ARG;
*(ULONG *)pParam=pCfg->BaseAddr;
return SDE_OK;
case SDC_GET_MAX_SIZE:
if(maxlen!=sizeof(ULONG))return SDE_INVALID_ARG;
*(ULONG *)pParam=pCfg->MaxSize;
return SDE_OK;
case SDC_WRITE_FLASH:
return write_intelflash(pDataBuf,pParam,maxlen);
case SDC_READ_FLASH:
return read_intelflash(pDataBuf,pParam,maxlen);
case SDC_ERASE_CHIP:
{
int ret=SDE_FLASH_FAIL;
return ret;
}
case SDC_ERASE_SECTOR:
{
ULONG offset=*(ULONG *)pParam;
int ret=SDE_OK;
ULONG i,ii;
ULONG BaseAddr=0xFFFFFFFF;
for(i=0;i<8 && pCfg->CSRange[i][1]!=0;i++)
if(pCfg->CSRange[i][0]<=offset &&
pCfg->CSRange[i][1]> offset){
BaseAddr=pCfg->CSRange[i][0]+pCfg->BaseAddr;
offset -= pCfg->CSRange[i][0];
}
if(BaseAddr==0xFFFFFFFF)return SDE_INVALID_ARG;
if(maxlen!=sizeof(ULONG))return SDE_INVALID_ARG;
if(offset <pCfg->UnitSize )
{
WriteReg(BaseAddr + 0x10,0x00900090);
for(i=0;i<0x50;i++);//wait Tida
i=ReadReg(BaseAddr + 0x04)&0x00000001;
WriteReg(BaseAddr,0x00ff00ff);
if( i== 1) /* Intel C3 flash 16-Bottom */
{
for(i=0;i<8;i++){
WriteReg(BaseAddr+ i*16*1024,0x00200020);
WriteReg(BaseAddr+ i*16*1024 ,0x00D000D0);
for(i=0;i<FLASH_ERASE_SECTOR_LOOP;i++){
if((ReadReg(BaseAddr+ i*16*1024)&0x00800080)==0x00800080)break;
}
if(i==FLASH_ERASE_SECTOR_LOOP)ret=SDE_FLASH_FAIL;
if((ReadReg(BaseAddr+ i*16*1024)&0x00380038) != 0)ret=SDE_FLASH_FAIL;
//ret= ReadReg(BaseAddr+ i*16*1024);
//if((ret&0x00380038) != 0);
WriteReg(BaseAddr+ i*16*1024,0x00ff00ff);
}
}
}
if(offset>=(pCfg->MaxSize - pCfg->UnitSize))
{
WriteReg(BaseAddr + 0x10,0x00900090);
for(i=0;i<0x50;i++);//wait Tida
i=ReadReg(BaseAddr + 0x04)&0x00000001;
WriteReg(BaseAddr,0x00ff00ff);
if(i == 0 ) /* Intel C3 flash 16-Top */
{
for(i=1;i<9;i++){
WriteReg(BaseAddr+(pCfg->MaxSize)- i*16*1024,0x00200020);
WriteReg(BaseAddr+(pCfg->MaxSize)- i*16*1024,0x00D000D0);
for(ii=0;ii<FLASH_ERASE_SECTOR_LOOP;ii++){
if((ReadReg(BaseAddr+(pCfg->MaxSize)- i*16*1024)&0x00800080)==0x00800080) break;}
if(i==FLASH_ERASE_SECTOR_LOOP)ret=SDE_FLASH_FAIL;
//ret=ReadReg(BaseAddr+(pCfg->MaxSize)- i*16*1024);
//if((ret&0x00380038) != 0);
if((ReadReg(BaseAddr+(pCfg->MaxSize)- i*16*1024)&0x00380038) != 0)ret=SDE_FLASH_FAIL;
WriteReg(BaseAddr+(pCfg->MaxSize)- i*16*1024,0x00ff00ff);
}
}
}
WriteReg(BaseAddr,0x00200020);
WriteReg(BaseAddr+offset,0x00D000D0);
for(i=0;i<FLASH_ERASE_SECTOR_LOOP;i++){
if((ReadReg(BaseAddr)&0x00800080)==0x00800080)break;
}
if(i==FLASH_ERASE_SECTOR_LOOP)ret=SDE_FLASH_FAIL;
if((ReadReg(BaseAddr)&0x00380038) != 0)ret=SDE_FLASH_FAIL;
//ret=ReadReg(BaseAddr);
//if((ret&0x00380038) != 0);
WriteReg(BaseAddr,0x00ff00ff);
return ret;
}
default:
return SDE_UNKNOW_CMD;
}
/* return SDE_OK; */
}
/*-------------------------------------------------------------------
this is one of the SDEV drivers external PORT
---------------------------------------------------------------------*/
char *Flash32BspInit(int DEV, char *FreeMemPtr, Flash32CfgStruct *cfg)
{
Flash32CfgStruct *pCfg=cfg;
ULONG BaseAddr=pCfg->BaseAddr;
ULONG UnitSize=pCfg->UnitSize;
ULONG MaxSize=pCfg->MaxSize;
ULONG i,ii,iii;
ULONG dwMCode,dwDCode;
/*Now read sst Product Identification*/
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00aa00aa);
WriteReg(BaseAddr+(ULONG)(0x2aaa<<2),0x00550055);
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00900090);
for(i=0;i<SST_ID_READ_WAIT;i++);//wait Tida
dwMCode=ReadReg(BaseAddr+(ULONG)(0x0<<2));
dwDCode=ReadReg(BaseAddr+(ULONG)(0x1<<2));
/*exit software ID read modes*/
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00aa00aa);
WriteReg(BaseAddr+(ULONG)(0x2aaa<<2),0x00550055);
WriteReg(BaseAddr+(ULONG)(0x5555<<2),0x00F000F0);
for(i=0;i<SST_ID_READ_WAIT;i++);//wait Tida
/*if the device is SST*/
if( (dwMCode==SST_MANUFACTURER_CODE) && (dwDCode==SST_DEVICE_CODE) )
{
InstallSD(DEV,NULL,NULL,SstFlash32Cntrl,FreeMemPtr);
}
else//If not sst,then st sharp and intel have the same operation
{
WriteReg(BaseAddr + 0x10,0x00900090); /*Read configration start! Example ID and MCIDS*/
for(i=0;i<0x50;i++);//wait Tida
dwMCode=ReadReg(BaseAddr+(ULONG)(0x0<<2));
dwDCode=ReadReg(BaseAddr+(ULONG)(0x1<<2));
WriteReg(BaseAddr,0x00ff00ff); /*Set the flash in read modes!*/
if(dwMCode==SHARP_MANUFACTURER_CODE && (dwDCode & 0xFFF0FFF0)==SHARP_DEVICE_CODE)//block erase is diference betweem sharp and intel s3
{
InstallSD(DEV,NULL,NULL,SharpFlash32Cntrl,FreeMemPtr);
}
else
{
if((dwMCode== INTEL_C3MANUFACTURER_CODE && (dwDCode & 0xFFF0FFF0)== INTEL_C3)|| /*Intel C3 flash 16-B */
(dwMCode== ST_MANUFACTURER_CODE && dwDCode == ST_M28W320CT_DEVICE_CODE)) /*ST flash 16-B */
{
InstallSD(DEV,NULL,NULL,IntelFlash32C3Cntrl,FreeMemPtr);
for(i = 0; i < (MaxSize/UnitSize); i++)
{
if(i==0 || i==(MaxSize/UnitSize)-1)
{
for(iii = 0; iii < 8; iii++)
{
WriteReg(BaseAddr+UnitSize*i +UnitSize/8*iii, 0x00600060);
for(ii=0;ii<FLASH_WRITE_LOOP;ii++)
{
if((ReadReg(BaseAddr+UnitSize*i +UnitSize/8*iii)&0x00800080)==0x00800080)
break;
}
WriteReg(BaseAddr+UnitSize*i +UnitSize/8*iii, 0x00d000d0);
for(ii=0;ii<FLASH_WRITE_LOOP;ii++)
{
if((ReadReg(BaseAddr+UnitSize*i +UnitSize/8*iii)&0x00800080)==0x00800080)
break;
}
WriteReg(BaseAddr+UnitSize*i +UnitSize/8*iii, 0x00ff00ff);
}
}
WriteReg(BaseAddr+UnitSize*i, 0x00600060);
for(ii=0;ii<FLASH_WRITE_LOOP;ii++){
if((ReadReg(BaseAddr+UnitSize*i)&0x00800080)==0x00800080)break;
}
WriteReg(BaseAddr+UnitSize*i, 0x00d000d0);
for(ii=0;ii<FLASH_WRITE_LOOP;ii++){
if((ReadReg(BaseAddr+UnitSize*i)&0x00800080)==0x00800080)break;
}
WriteReg(BaseAddr+UnitSize*i, 0x00ff00ff);
}
}
else
InstallSD(DEV,NULL,NULL,IntelFlash32Cntrl,FreeMemPtr);
}
}
if(cfg->CSRange[0][1]==0)cfg->CSRange[0][1]=cfg->MaxSize;
Flash32Init(FreeMemPtr, cfg);
FreeMemPtr += sizeof(Flash32CfgStruct);
memcpy(FreeMemPtr,"*Flsh32Dat",8);
FreeMemPtr += 8;
return FreeMemPtr;
}
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