/* @(#) pSOSystem/PPC V221 */
/***********************************************************************/
/*                                                                     */
/*   MODULE:  mpc8xx/sdev/fpgacfg.c                                    */
/*   DATE:    2000/2/22                                                */
/*   AUTHOR:  Dong Aiping                                              */
/*   PURPOSE:                                                          */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*           Copyright 1999 - 2000, ZHONGXING TELECOM CO.,LTD.         */
/*                      ALL RIGHTS RESERVED                            */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*  Express Mode uses an eight-bit-wide bus path for fast confuguration
    of Xilinx FPGAs. Its limit is no CRC verification. So we use the 
    Slave Serial Mode to configure the Volt SpartanXL family.  
    
    The Xilinx devices are 100% pretested and the XC4000 series LCA 
    devices can use Cyclic Redundancy Checking (CRC) on the configura-
    tion bitstream to check the integrity of the bitstream loaded into
    the LCA configuration memory.  
    
    The configuration data file is a special bitstream file. This file
    is create by specifying a BitGen option in the Xinlinx development
    software. Note that presently, the software only supports this 
    option using command line entry. The following command produces a
    configuration file for Slave Serial Mode:
        bitgen -g CRC:enable -b -w filename
                                                                       */
/***********************************************************************/



#include "fpgacfg.h"

/*======================================================================
*   FUNCTION NAME: delay_us
*   DESCRIPTION:   Delay 1 us  
*   INPUT:         us_num : the number of us Times
*   OUTPUT:        
*   NOTE:      Current CPU speed is  24M, if your cpu speed is changed ,
*              you must change this function .                                                            
*=======================================================================*/
void delay_us(ULONG us_num)
{   
    ULONG i;
    volatile ULONG temp;
    for(i=0;i<us_num;i++){
        temp = 7;
        temp += 7;
    }
}
/*======================================================================
*   FUNCTION NAME: FPGA_Config 
*   DESCRIPTION: FPGA Configuration Process, 4 steps    
*   INPUT:       *pFpgaData - The pointer of FPGA data file 
*                DataLen    - The length  of FPGA data file     
*   OUTPUT:      TRUE       - FPGA Config Success
*                FALSE      - FPGA Config Failure  
*   NOTE:                                                              
*=======================================================================*/
int FPGA_Config(UCHAR *pFpgaData, ULONG DataLen)
{
    UCHAR    byTemp;
    ULONG    WaitCount=0,ByteCount,BitCount;
    
    /*-------< Memory Clear >-----------------------*/
    FPGA_SetPin(FPGA_PROGRAM,1);
    FPGA_SetPin(FPGA_PROGRAM,0);
    FPGA_SetPin(FPGA_PROGRAM,1);
    /*-------< Initialization >---------------------*/
    while (!(FPGA_GetPin(FPGA_INIT))) {
        WaitCount++;
        delay_us(1);
        if (WaitCount>1000) return (FALSE);
    }
    delay_us(10);
    
    /*-------< Configuration >-----------------------*/
    for(ByteCount=0;ByteCount<DataLen;ByteCount++)
    {
         byTemp=(*pFpgaData++); 
         for (BitCount=0;BitCount<8;BitCount++) {
             /* if your CPU speed is too high, 
                you should add some delay_time here. 
                The highest frequence is 1MHZ.       */
             FPGA_WriteBit((byTemp<<BitCount)&0x80);
         }
         if(!(FPGA_GetPin(FPGA_INIT))) break;
    }
    
    /*-------< Start_up >----------------------------*/
    if (!(FPGA_GetPin(FPGA_DONE))) 
        return (FALSE);
    else
        return (TRUE);
}