?? bdcomm.c
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/* @(#) pSOSystem PowerPC/V2.2.2*/
/***********************************************************************/
/* */
/* MODULE: bsps/fuc8xx/src/board.c */
/* DATE: 98/07/02 */
/* AUTHOR: Shan Zhengguang */
/* PURPOSE: Board-level code */
/* */
/*---------------------------------------------------------------------*/
/* */
/* Copyright 1998 - 1999, ZHONGXING TELECOM CO.,LTD. */
/* ALL RIGHTS RESERVED */
/* */
/*---------------------------------------------------------------------*/
/* */
/* The routines in this module performs board-level functions. */
/* */
/***********************************************************************/
#include "bsp.h"
#include <bspfuncs.h>
#include <configs.h>
#include <machine.h>
#include "board.h"
#include "bdcomm.h"
#define STATIC static
unsigned long PBMap,PBMask;
unsigned short PAMap,PAMask;
unsigned short PCMap,PCMask;
unsigned short PDMap,PDMask;
/***********************************************************************/
/* Function Prototypes */
/***********************************************************************/
void BspDisableDataCache(void);
void BspDisableInstCache(void);
void BspSyncUpCaches(void);
ULONG BspGetDramSpeed(void);
ULONG BspGetDramSize(void);
void BspPmontCallout(void (*)(), void (*)());
unsigned long ClrAbortInt (void);
/***********************************************************************/
/* External Declarations */
/***********************************************************************/
extern void SysDCacheFlush(void *, ULONG);
extern void SysHandlerInit(void);
extern void Sys_Cache_Init(void);
extern void LanStop(void);
extern ULONG ppcPVRrd(void);
extern void dpram_init(void);
extern ULONG Print(char *format, ...);
/***********************************************************************/
/* Global Variable Declarations */
/***********************************************************************/
ULONG BoardDecClkRateHz;
/***********************************************************************/
/* The node anchor address is a pointer to the node configuration */
/* table, which in turn points to the pSOS+ configuration table. This */
/* driver will look in the pSOS+ configuration table to see how many */
/* ticks per second are specified, and thus how many interrupts per */
/* second to generate. */
/***********************************************************************/
extern NODE_CT *anchor;
/* External Exception Store -- by chenjun*/
void (*ExceptionStore)();
ExcepRegInfoStruct ExcepRegInfo;
ULONG ExcepStack[60];
/***********************************************************************/
/* PowerQUICC mapping table. */
/* */
/* This table maps the port number to the correct QUICC chip. */
/* This table should be expanded by sets of four for each MPC8xx in */
/* the system, this table is used in a Master, Slave configuration. */
/***********************************************************************/
const ULONG quicc_num[MAX_SCC] =
{
0, /* MASTER SCC #1 */
0, /* MASTER SCC #2 */
0, /* MASTER SCC #3 */
0 /* MASTER SCC #3 */
};
/***********************************************************************/
/* SCC Identification table. */
/* */
/* This table is used to map a port number to a PowerQUICC SCC number */
/* When more than one PowerQUICC is used, the port number ranges */
/* from 0 to MAX_SCC - 1 while the entries in this table can never be */
/* higher than 3. */
/***********************************************************************/
const ULONG scc_num[MAX_SCC] =
{
0, /* MASTER SCC #1 */
1, /* MASTER SCC #2 */
2, /* MASTER SCC #3 */
3 /* MASTER SCC #4 */
};
/***********************************************************************/
/* DPRAM base address mapping table. */
/* */
/* This table is used to determine the DPRAM base address of a */
/* given port. */
/***********************************************************************/
const ULONG dpram_base[MAX_SCC] =
{
M_DPRAM_BASE, /* MASTER SCC #1 */
M_DPRAM_BASE, /* MASTER SCC #2 */
M_DPRAM_BASE, /* MASTER SCC #3 */
M_DPRAM_BASE /* MASTER SCC #4 */
};
/***********************************************************************/
/* SMC port number mapping table */
/***********************************************************************/
const ULONG SmcNum[MAX_SMC] = {
0,
1
};
/***********************************************************************/
/* Baud rate generator allocation table */
/***********************************************************************/
const ULONG AllocBrg[MAX_SMC] = {
0,
1
};
/***********************************************************************/
/* IO Pins and IRQ Pins configuration */
/***********************************************************************/
/* TURE=1 is defined in MPC8XX.H */
void SetupIOI(void)
{
int i;
ULONG bit,dat;
PAMap=S_PortADataReg; PAMask=0xFFFF;
PBMap=S_PortBDataReg; PBMask=0xFFFFFFFF;
PCMap=S_PortCDataReg; PCMask=0xFFFF;
PDMap=S_PortDDataReg; PDMask=0xFFFF;
for(i=0;i<MAX_IOI_ENTRIES;i++)
{
if(IOIPinMap[i].available!=TRUE)continue;
bit=IOIPinMap[i].bit;
dat=IOIPinMap[i].dat;
switch(IOIPinMap[i].port)
{
case PORTA:
if(bit>=0 && bit <=15)
{
if(dat==1 || dat==0) SET_PA_BIT(bit,dat);
if(IOIPinMap[i].dir!=0) SET_BIT(S_PortADataDirReg,bit,16)
else CLR_BIT(S_PortADataDirReg, bit,16)
if((bit>=8 && bit<=12) || bit==14)
{
if(IOIPinMap[i].odr==0) CLR_BIT(S_PortAOpenDrainReg,bit,16)
else SET_BIT(S_PortAOpenDrainReg,bit,16)
}
if(IOIPinMap[i].par!=0) SET_BIT(S_PortAPinAssgmntReg,bit,16)
else CLR_BIT(S_PortAPinAssgmntReg, bit,16)
}
break;
case PORTB:
if(bit>=14 && bit <=31)
{
if(dat==1 || dat==0) SET_PB_BIT(bit,dat);
if(IOIPinMap[i].dir!=0)SET_BIT(S_PortBDataDirReg,bit,32)
else CLR_BIT(S_PortBDataDirReg, bit,32)
if(bit>=16 && bit<=31)
{
if(IOIPinMap[i].odr==0) CLR_BIT(S_PortBOpenDrainReg,bit,32)
else SET_BIT(S_PortBOpenDrainReg,bit,32)
}
if(IOIPinMap[i].par!=0) SET_BIT(S_PortBPinAssgmntReg,bit,32)
else CLR_BIT(S_PortBPinAssgmntReg, bit,32)
}
break;
case PORTC:
if(bit>=4 && bit <=15)
{
if(dat==1 || dat==0) SET_PC_BIT(bit,dat);
if(IOIPinMap[i].dir!=0)SET_BIT(S_PortCDataDirReg,bit,16)
else CLR_BIT(S_PortCDataDirReg, bit,16)
if(IOIPinMap[i].so !=0 ) SET_BIT(S_PortCSpecialOptsReg,bit,16)
else CLR_BIT(S_PortCSpecialOptsReg, bit,16)
if(IOIPinMap[i].inttype==IHL)SET_BIT(S_PortCIntCtrlReg,bit,16)
else CLR_BIT(S_PortCIntCtrlReg, bit,16)
if(IOIPinMap[i].par!=0) SET_BIT(S_PortCPinAssgmntReg,bit,16)
else CLR_BIT(S_PortCPinAssgmntReg, bit,16)
}
break;
case PORTD:
if(bit>=3 && bit <=15)
{
if(dat==1 || dat==0) SET_PD_BIT(bit,dat);
if(IOIPinMap[i].dir!=0)SET_BIT(S_PortDDataDirReg,bit,16)
else CLR_BIT(S_PortDDataDirReg, bit,16)
if(bit==8)
{
if(IOIPinMap[i].odr!=0 ) SET_BIT(S_PortDDataDirReg,0,16)
else CLR_BIT(S_PortDDataDirReg, 0,16)
}
else if(bit==10)
{
if(IOIPinMap[i].odr!=0 ) SET_BIT(S_PortDDataDirReg,1,16)
else CLR_BIT(S_PortDDataDirReg, 1,16)
}
if(IOIPinMap[i].par!=0) SET_BIT(S_PortDPinAssgmntReg,bit,16)
else CLR_BIT(S_PortDPinAssgmntReg, bit,16)
}
break;
}/* end of switch(available) */
}/* end of for(MAX_IOI_ENTRIES)*/
PAMask=(~S_PortAPinAssgmntReg)&S_PortADataDirReg;
PBMask=(~S_PortBPinAssgmntReg)&S_PortBDataDirReg;
PCMask=(~S_PortCPinAssgmntReg)&S_PortCDataDirReg;
PDMask=(~S_PortDPinAssgmntReg)&S_PortDDataDirReg;
}/* end of SetupIOI()
/***********************************************************************/
/* BspDisableDataCache: Flushes the Data cache and disables it, this */
/* routine is called to flush and disable the data*/
/* cache, and to turn off the MMU */
/* */
/* RETURNS: NONE */
/* */
/***********************************************************************/
void
BspDisableDataCache()
{
#if (BRD_DCACHE == YES) || (BSP_MMU == YES)
ULONG OldIpl;
OldIpl = splx(MAX_ILEV);
#if (BRD_DCACHE == YES)
FlushDcache();
SysDcacheInhibit();
#endif
#if (BSP_MMU == YES)
BspMmuTransOff();
#endif
splx(OldIpl);
#endif /* (BRD_DCACHE == YES) || (BSP_MMU == YES) */
}
/***********************************************************************/
/* BspDisableInstCache: Disables the Instruction cache */
/* */
/* RETURNS: NONE */
/* */
/***********************************************************************/
void
BspDisableInstCache()
{
#if (BRD_ICACHE == YES)
ULONG OldIpl;
OldIpl = splx(MAX_ILEV);
SysIcacheInhibit();
splx(OldIpl);
#endif
}
/***********************************************************************/
/* BspSyncUpCaches: Flushes the Data cache and Invalidates the I-Cache */
/* */
/* RETURNS: NONE */
/* */
/***********************************************************************/
void
BspSyncUpCaches()
{
#if (BRD_DCACHE == YES) || (BRD_ICACHE == YES)
ULONG OldIpl;
OldIpl = splx(MAX_ILEV);
#if (BRD_DCACHE == YES)
FlushDcache();
SysDcacheInv(0, BD_SIZE_OF_DCACHE);
#endif
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