#if (BRD_ICACHE == YES)
        SysIcacheInv(0, BD_SIZE_OF_ICACHE);
#endif
        splx(OldIpl);
#endif /* (BRD_DCACHE == YES) || (BRD_ICACHE == YES) */

}
/***********************************************************************/
/* BspCpuClkRate: Return the processor clock speed in multiple of MHz  */
/*                                                                     */
/* INPUTS:  None                                                       */
/* OUTPUTS: Returns the current cpu clock rate                         */
/*                                                                     */
/***********************************************************************/
ULONG        
BspCpuClkRate(void)
{
        return
            (bspGetInputClkHz() * ((S_PLL_ControlReg >> 20) + 1)) / 1000000;
}
/***********************************************************************/
/*  BspRamBase: Return starting/base address of RAM (as seen by CPU)   */
/*                                                                     */
/*     RETURNS: starting address of onboard DRAM                       */
/*     NOTE(S):                                                        */
/*                                                                     */
/***********************************************************************/
unsigned long BspRamBase(void)
{
        return BD_DRAM_BASE_ADDR;
}

/***********************************************************************/
/* Local function to get the size of the DRAM installed on the board   */
/***********************************************************************/
ULONG
BspGetDramSize(void)
{
        return(BD_DRAM_SIZE);
}

/***********************************************************************/
/*     RamSize: Return the amount of DRAM installed on the board       */
/*                                                                     */
/*     RETURNS: The size of DRAM SIMMs in bytes                        */
/*        NOTE: Returns 0 if SIM type not recognized                   */
/*                                                                     */
/***********************************************************************/
ULONG RamSize(void)
{
        return(BD_DRAM_SIZE);
}
ULONG BspCpuRev()
{
        return( GetIMMR() & CPU_REV_MASK);
}

/***********************************************************************/
/* ClrAbortInt: Clear interrupt signal after abort interrupt.          */
/*                                                                     */
/***********************************************************************/
unsigned long ClrAbortInt(void)
{
    /* do not fool with interrupts mask, pSOS can be screwed up if do */
    Print("\n    !!!! ABORT Button Pressed !!!!\n");
    return 0;
}

/***********************************************************************/
/* SysInitFail: Report a system initalization failure                  */
/*                                                                     */
/*      INPUTS: string = Pointer to text of message                    */
/*                                                                     */
/*        NOTE: Doesn't return.  Just continually prints the error     */
/*              message on the serial channel once per second.         */
/*                                                                     */
/***********************************************************************/
void SysInitFail(const char *string)
{
const char *ptr;
int i;
 
#if        BSP_NEW_SERIAL
    ProbeIOInit();
    for (;;)
        {
        ptr = string;
        while (*ptr)
            ProbeConout(*ptr++);
        ProbeConout('\n');
        ProbeConout('\r');
        for (i = 1; i <= 10; i++)
            Delay100ms();
        }                                           
#else
        Delay100ms();
        SerialSetup(9600, 1, 0);
        SerialPollInit();
        Delay100ms();
        for (;;)
            {
            ptr = string;
            while (*ptr)
                SerialPollConout(*ptr++);
            SerialPollConout('\n');
            SerialPollConout('\r');
            for (i = 1; i <= 10; i++)
                Delay100ms();
            }
#endif
}

/***********************************************************************/
/* InitBoard: Perform board initialization.                            */
/*                                                                     */
/***********************************************************************/
void InitBoard(void)
{
int   Var;
ULONG cpu_speed;
SET_PC_BIT(14,1); 
resetSWT();
SET_PC_BIT(13,1);
/*---------------------------------------------------------------------*/
/* Issue CP reset command so RISC re-initializes its internal state.   */
/*---------------------------------------------------------------------*/
S_CP_CommandReg = CPM_SW_RESET + SEMAPHORE_FLAG;

/*---------------------------------------------------------------------*/
/* Reset the RISC processor control                                    */
/*---------------------------------------------------------------------*/
S_RISC_ConfigReg = 0;

/*---------------------------------------------------------------------*/
/* Disable all SIU interrupts                                          */
/*---------------------------------------------------------------------*/
S_SiMaskRegister = 0x0;  

/*---------------------------------------------------------------------*/
/* Clear the entire Dual-Ported RAM.                                   */
/*---------------------------------------------------------------------*/
for (Var = 0x000; Var <= 0x1000; ++Var)
    *(volatile UCHAR *)(M_DPRAM_BASE + Var) = 0;
 
/*---------------------------------------------------------------------*/
/* Note: PLL Cotrol register is now set HdwInitDRAM if run in ROM.     */ 
/* for RAM code we just the value set in ROM.                          */
/*---------------------------------------------------------------------*/

/*---------------------------------------------------------------------*/
/* Calculate the time constant. The decrementer decrements once every  */
/* four input clocks (bspGetInputClkHz()).                             */
/* i.e. timeconst = (bspGetInputClkHz()) / (4 * ticks2sec)             */
/*---------------------------------------------------------------------*/
#if ( BD_CPU_SPEED*1000000/BD_INPUT_CLOCK )<=2
BoardDecClkRateHz = (bspGetInputClkHz() / 16 );
#else
BoardDecClkRateHz = (bspGetInputClkHz() / 4 );
#endif

 
/*---------------------------------------------------------------------*/
/* Setup the MPC860 Input,Output,Interrupt Leaders configuration       */
/*---------------------------------------------------------------------*/
SetupIOI();

/*---------------------------------------------------------------------*/
/* Disable the ethernet interface                                      */
/*---------------------------------------------------------------------*/
#if (BSP_LAN1 == YES)
LanStop();
#endif

/*---------------------------------------------------------------------*/
/* Issue CP reset command so RISC re-initializes its internal state.   */
/*---------------------------------------------------------------------*/
S_CP_CommandReg = CPM_SW_RESET + SEMAPHORE_FLAG;
while (S_CP_CommandReg & SEMAPHORE_FLAG);


/*---------------------------------------------------------------------*/
/* Configure the Master CPM Interrupt Controller                       */
/*---------------------------------------------------------------------*/
S_CP_IntConfigReg =
   /*
   ** Set the CPM interrupt priority.
   */
   (CPM_IRQ_LEVEL << 13)

   /*
   ** Declare the highest priority CPM interrupt.
   */
   + (0x1F << 8)

   /*
   ** Establish the SCC priority spread scheme.
   */
   + GROUPED

   /*
   ** Enable the CPM Interrupts.
   */
   +CPM_EN_INTS;

S_SCC1MaskReg  = 0;
S_SCC1EventReg = 0xFFFF;
S_SCC2MaskReg  = 0;
S_SCC2EventReg = 0xFFFF;
S_SMC1MaskReg = 0;
S_SMC2MaskReg = 0;

/*---------------------------------------------------------------------*/
/* Set-up the shared dual ported memory bit map.                       */
/*---------------------------------------------------------------------*/
dpram_init();

/*---------------------------------------------------------------------*/
/* Enable Caches according to the specified mode in board.h            */
/*                                                                     */
/* The instruction cache is only turned on for REV A or greater chips. */
/* The mmu and data cache are not supported.                           */
/*---------------------------------------------------------------------*/
#if (BRD_ICACHE == YES) && (BSP_MMU == NO)
if ((GetIMMR() & 0x00FF) >= REVA)  /* Enable for chips REV A or greater */
   SysIcacheInit();
#endif
 
/*---------------------------------------------------------------------*/
/* Setup the vector table                                              */
/*---------------------------------------------------------------------*/
vectorSetup();

/*---------------------------------------------------------------------*/
/* Initilize the interrupt handler (must be done before enabling any   */
/* interrupts.                                                         */
/*---------------------------------------------------------------------*/
IsrHandlerInit(0);

/*---------------------------------------------------------------------*/
/* Enable CPM interrupt level                                          */
/*---------------------------------------------------------------------*/
S_SiMaskRegister =  SIU_ILEV_MASK_BIT(CPM_IRQ_LEVEL);  

/*---------------------------------------------------------------------*/
/* Enable the LAN on the Board.                                        */
/*---------------------------------------------------------------------*/
#if (BSP_LAN1 == YES)
LanEnable();
#endif

BoardSpecInit();

InitTDM();
SET_PC_BIT(5,1);
resetSWT();
SysInit();
}

/* miscillenious function for board */

void initTBSCR(void)
{
        PDA  *pda;
        pda = (PDA *)(GetIMMR() & IO_MAP_MASK);
        if((pda->simt_tbscr & 0x1)!=0x1)
                pda->simt_tbscr=1;
}


unsigned long  getTimeBaseClock(void)
{
#if ( BD_CPU_SPEED*1000000/BD_INPUT_CLOCK )<=2
        return (BD_INPUT_CLOCK>>4);
#else
        return (BD_INPUT_CLOCK>>2);
#endif
}

unsigned long getResetStatusReg(void)
{
        PDA  *pda;
        pda = (PDA *)(GetIMMR() & IO_MAP_MASK);
        return pda->clkr_rsr;
}

void resetSWT(void){
        PDA  *pda;
        pda = (PDA *)(GetIMMR() & IO_MAP_MASK);
	SPLX(pda->siu_swsr=0x556c; pda->siu_swsr=0xaa39; )
}

void disableSWT(void){
        PDA  *pda;
        pda = (PDA *)(GetIMMR() & IO_MAP_MASK);
        pda->siu_sypcr=0xffffff88;
}

void enableSWT(void){
        PDA  *pda;
        pda = (PDA *)(GetIMMR() & IO_MAP_MASK);
        pda->siu_sypcr=0xffffff8f;
}

unsigned long readSWT(void)
{
        PDA  *pda;
        pda = (PDA *)(GetIMMR() & IO_MAP_MASK);
        return (unsigned long)(pda->siu_sypcr);
}