/* @(#) pSOSystem PowerPC/V2.2.2*/
/***********************************************************************/
/*                                                                     */
/*   MODULE:  bsps/fuc8xx/src/mmumap.c                                 */
/*   DATE:    97/07/03                                                 */
/*   PURPOSE: Memory Managment Unit (MMU) mapping module               */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*           Copyright 1998 - 1999, ZHONGXING TELECOM CO.,LTD.         */
/*                      ALL RIGHTS RESERVED                            */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*   The Memory Managment Unit provides translation of effective       */
/*   addresses generated by the fix-point unit or instruction prefetch */
/*   unit into physical address. The MMU also provides cache control   */
/*   for the split code and data cache (like write-through or write-   */
/*   back policies).                                                   */ 
/*                                                                     */
/***********************************************************************/
#include <bspfuncs.h>
#include <icontrol/mpc8xx.h>
#include <serial/smc8xx.h>
#include <lan/lan8xx.h>
#include <machine.h>
#include "../bsp.h"
#include "board.h"
#include <icontrol/mmu8xx.h>
#include <icontrol/pda8xx.h>
#include <pna.h>

#include "sdev.h" /*add by py*/
/***********************************************************************/
/* Local Function Prototypes                                           */
/***********************************************************************/
void MapRegions(void);
void BrdBufDisCacheing(void);

/***********************************************************************/
/* Extern functions                                                    */
/***********************************************************************/
extern void MapVir2RealAddr(UCHAR *VirAddr, UCHAR *RealAddr, ULONG Size, 
                            PAGE_T Attributes, ULONG cachePolic);
void   DisCacheing(UCHAR *VirAddr, ULONG Size, UCHAR Cache);

/***********************************************************************/
/* Global variables                                                    */
/***********************************************************************/
#if (BSP_LAN1 == YES)
extern ULONG  NrTxHdrs;         /* Number of transmit headers */
extern TX_HDR TxHeaders[];      /* The actual headers */
extern UCHAR  RxBuffs[];        /* Receive buffer for lan driver */
extern UCHAR *DummyVar;
#endif

#if (BSP_NEW_SERIAL == YES)
#if BSP_MMU==YES	
extern UCHAR  *gGsBlkArea;      /* GS blocks start address size */
extern ULONG  gGsBlkAreaSize;   /* GS block size in bytes */
extern chan_control channels[]; /* smc8xx channel control structure */
#endif
#else
#define RX_BUF_SIZE     128
#define TX_BUF_SIZE     64
extern  char Smc1_RxChars[];
extern  char Smc2_RxChars[];
extern  char Smc1_TxChars[];
extern  char Smc2_TxChars[];
extern  UCHAR *SerialDummy;
#endif

/***********************************************************************/
/* MapRegions(void): Map the memory and IO regions on the ADS8xx board */ 
/***********************************************************************/
void
MapRegions(void)
{
        PDA    *IOMemMap;
	PAGE_T	Page;
	UCHAR  *Addr;
	ULONG	cachePolicy;

	cachePolicy = CACHE_WRITE_BACK;

        /* Get the pointer to Internal Memory Map */
        IOMemMap = (PDA *)(GetIMMR() & IO_MAP_MASK);

#if ( CS0_SIZE != 0 )
        	Page.Word = CS0_ATTR;
        	MapVir2RealAddr((UCHAR *)CS0_BASE,(UCHAR *)CS0_BASE,CS0_SIZE,
				Page, cachePolicy);
#endif

#if ( CS1_SIZE != 0 )
		Page.Word = CS1_ATTR;
        	MapVir2RealAddr((UCHAR *)CS1_BASE,(UCHAR *)CS1_BASE,CS1_SIZE,
				Page, cachePolicy);
#endif

#if ( CS2_SIZE != 0 )
		Page.Word = CS2_ATTR;
        	MapVir2RealAddr((UCHAR *)CS2_BASE,(UCHAR *)CS2_BASE,CS2_SIZE,
				Page, cachePolicy);
#endif

#if ( CS3_SIZE != 0 )
		Page.Word = CS3_ATTR;
        	MapVir2RealAddr((UCHAR *)CS3_BASE,(UCHAR *)CS3_BASE,CS3_SIZE,
				Page, cachePolicy);
#endif

#if ( CS4_SIZE != 0 )
		Page.Word = CS4_ATTR;
        	MapVir2RealAddr((UCHAR *)CS4_BASE,(UCHAR *)CS4_BASE,CS4_SIZE,
				Page, cachePolicy);
#endif

#if ( CS5_SIZE != 0 )
		Page.Word = CS5_ATTR;
        	MapVir2RealAddr((UCHAR *)CS5_BASE,(UCHAR *)CS5_BASE,CS5_SIZE,
				Page, cachePolicy);
#endif

#if( CS6_SIZE != 0 )
		Page.Word = CS6_ATTR;
        	MapVir2RealAddr((UCHAR *)CS6_BASE,(UCHAR *)CS6_BASE,CS6_SIZE,
				Page, cachePolicy);
#endif

#if ( CS7_SIZE != 0 )
		Page.Word = CS7_ATTR;
        	MapVir2RealAddr((UCHAR *)CS7_BASE,(UCHAR *)CS7_BASE,CS7_SIZE,
				Page, cachePolicy);
#endif

        /*
	 * Mapin the Internal I/O mappped register and Dual-Port
	 * Ram with Cache-Inhibited mode.
         */
        Page.Word               = 0;    /* clear all bits */
        Page.Bit.PageProtMode   = 2;    /* inst: exec/exec, data: rw/rw */
        Page.Bit.PageChangeBit  = 1;    /* changeable pages */
        Page.Bit.PageAccessMode = 0x0c; /* hit for privileged state */
        Page.Bit.PageCacheDis   = 1;    /* Cache inhitbited */
        Page.Bit.PageValid      = 1;    /* page is valid */
 
        Addr = (UCHAR *)IOMemMap;
        MapVir2RealAddr(Addr, Addr, BD_IO_SIZE, Page, cachePolicy);
}

/**************************************************************************/
/* BrdBufDisCacheing(void): Board dependent function to disable cacheing  */
/**************************************************************************/
#include "sdev.h"
void
BrdBufDisCacheing(void)
{
#ifdef USE_UNCACHE_SECTION
	extern char UncacheBgn[], UncacheEnd[], Uncache2Bgn[], Uncache2End[];
        /* Disable/Enable cacheing of SMC IO buffer */
#if BSP_NEW_SERIAL
	#if BSP_MMU == YES
	DisCacheing(gGsBlkArea, gGsBlkAreaSize, CACHE_OFF);
	#endif
#endif
		DisCacheing(UncacheBgn,UncacheEnd-UncacheBgn,CACHE_OFF);
		DisCacheing(Uncache2Bgn,Uncache2End-Uncache2Bgn,CACHE_OFF);
#else /* for version 1.0 */

#if BSP_NEW_SERIAL
	#if BSP_MMU == YES
	DisCacheing(gGsBlkArea, gGsBlkAreaSize, CACHE_OFF);
	DisCacheing((UCHAR *)&channels[0], sizeof(chan_control)*MAX_SMC,
                     CACHE_OFF);
	#endif
#endif
#if (BSP_LAN1 == YES)
        /* Disable cacheing for the LAN driver */
        DisCacheing((UCHAR*)&RxBuffs[0], RXSIZE * NR_RXBUFFS, CACHE_OFF);
        DisCacheing((UCHAR*)&TxHeaders[0], sizeof(TX_HDR)*NrTxHdrs, CACHE_OFF);
        DisCacheing((UCHAR*)&DummyVar, PAGE_SIZE*1, CACHE_OFF);
#endif
        DisCacheing( UncachedBuffer,MAX_UNCACHED_BUFFER_LEN,CACHE_OFF);
#endif
}