/* @(#) pSOSystem PowerPC/V2.2.2: bsps/devices/icontrol/cpm8intr.c 2.4 97/09/26 08:52:39 */
/***********************************************************************/
/*                                                                     */
/*   MODULE:  bsps/devices/icontrol/cpm8intr.c                         */
/*   DATE:    97/09/26                                                 */
/*   PURPOSE: CPM interrupt hanling for MPC8xx processor.              */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*                                                                     */
/*          Copyright 1991 - 1997, Integrated Systems, Inc.            */
/*                      ALL RIGHTS RESERVED                            */
/*                                                                     */
/*   Permission is hereby granted to licensees of Integrated Systems,  */
/*   Inc. products to use or abstract this computer program for the    */
/*   sole purpose of implementing a product based on Integrated        */
/*   Systems, Inc. products.   No other rights to reproduce, use,      */
/*   or disseminate this computer program, whether in part or in       */
/*   whole, are granted.                                               */
/*                                                                     */
/*   Integrated Systems, Inc. makes no representation or warranties    */
/*   with respect to the performance of this computer program, and     */
/*   specifically disclaims any responsibility for any damages,        */
/*   special or consequential, connected with the use of this program. */
/*                                                                     */
/***********************************************************************/
#include <types.h>
#include <bspfuncs.h>
#include <icontrol/mpc8xx.h>
#include <powerpc/isrppc.h>
#include "board.h"
#include "bsp.h"

/*---------------------------------------------------------------------*/
/* Symbol Definitions                                                  */
/*---------------------------------------------------------------------*/
#define MAX_CPM_HNDLRS     32      /* Maximum # of interrupt  handlers */


/*---------------------------------------------------------------------*/
/* Table of the CPM interrupt handlers                                 */
/*---------------------------------------------------------------------*/
static ISR_HDNL_ENTRY CpmIsrEntry[MAX_CPM_HNDLRS];
void (*CpmIntrDefaultHandler)(long);


/***********************************************************************/
/* CpmIntrHandler: main interrupt handler for CPM interrupts            */
/*                                                                     */
/*      INPUTS: none                                                   */
/*       NOTES: The IsrMain() calls this routine to handle all CPM     */
/*              interrupts.                                            */
/*                                                                     */
/***********************************************************************/
void CpmIntrHandler(void * dummy)
{
    ULONG ivec;
    ULONG s;
    
    /* dummy=dummy; */
    
    /*----------------------------------------------------------------*/
    /* Acknowledge the interrupt and get the vector.                  */
    /*----------------------------------------------------------------*/
    S_CP_IntVectorReg = 0x01;
    ivec =  S_CP_IntVectorReg ;
    ivec = ivec >> 11;

    /*----------------------------------------------------------------*/
    /* At this point, the CPM to SIU interrupt is masked off via      */
    /* SIMASK register and the CPU interrupt is enabled in IsrMain(). */
    /* The current CPM device interrupt (e.g. SMC or SCC interruots)  */
    /* was acknowledged above. By the acknowledgement, all CPM device */
    /* interrupts which have the same or lower priorities are masked  */
    /* off and they will be enabled again when the bit in the CISR    */
    /* (CP In-servcie register) cleared. The bit related to CPM       */
    /* interrupt in the SIPEND is also cleared through the            */
    /* acknowledgement.                                               */        
    /*                                                                */
    /* To allow the CPM device with the higher priorities to be       */
    /* handled (supporting of nested CPM interrupts), we have to set  */
    /* the mask bit in SIMASK register for CPM.                       */
    /*----------------------------------------------------------------*/
    s = splx(MAX_ILEV);
    S_SiMaskRegister |= SIU_ILEV_MASK_BIT(CPM_IRQ_LEVEL);
    splx(s);

    if (CpmIsrEntry[ivec].isr_handler) {
        (*CpmIsrEntry[ivec].isr_handler)(CpmIsrEntry[ivec].arg);

    }
    else if(CpmIntrDefaultHandler) 
         (*CpmIntrDefaultHandler)(ivec);

    /*---------------------------------------------------------------*/
    /* Disable the CPM interrupt and then clear the in-servcie bit.  */
    /*---------------------------------------------------------------*/
    s = splx(MAX_ILEV);
    S_SiMaskRegister &= ~(SIU_ILEV_MASK_BIT(CPM_IRQ_LEVEL));
    splx(s);

    /*---------------------------------------------------------------*/
    /* clear the in-servcie bit.                                     */
    /*---------------------------------------------------------------*/
    S_CP_InServiceReg = 1 << ivec;

}


/***********************************************************************/
/* CpmIsrAddhHandler: Set up the ISR in the CPM Interrupt Table        */
/*                                                                     */
/* Purpose: To add a handler for CPM devices, i.e SCCs, SMCs, etc.     */
/*          Not to be used for external devices hooked to SIU's IRQ    */
/*          lines.                                                     */
/*                                                                     */
/*     INPUTS: vector number, default Handler address                  */
/*     NOTE(S):                                                        */
/*                                                                     */
/***********************************************************************/
long CpmIsrAddHandler(ULONG vector, void *handler, void * arg)
{

    /*-----------------------------------------------------------------*/
    /* Update Interrupt Handler Table with ISR address                 */
    /*-----------------------------------------------------------------*/
    vector -= CPM_VECT_BASE;
    if(vector < MAX_CPM_HNDLRS) {
        CpmIsrEntry[vector].isr_handler = (void (*)(void *)) handler;
        CpmIsrEntry[vector].arg = arg;
        return 0;
        }
    else
        return -1;
}

/***********************************************************************/
/* CpmIsrDelHandler: delete the interrupt handler.                     */
/***********************************************************************/
long CpmIsrDelHandler(ULONG vector, void *handler, void * arg)
{
    return 0;
}

/***********************************************************************/
/* CpmIsrInit: Set the default interrupt vector                        */
/*                                                                     */
/*      INPUTS: Default Handler address                                */
/*     NOTE(S):                                                        */
/*                                                                     */
/***********************************************************************/
void CpmIsrInit(void (*handler)(long))
{
    register ULONG i;
 
    for (i = 0; i < MAX_CPM_HNDLRS; i++) {
        CpmIsrEntry[i].isr_handler = 0;
        CpmIsrEntry[i].next = 0;
        }
    
    CpmIntrDefaultHandler = handler;
    IsrAddHandler(SIU_ILEV_TO_PRIORITY(CPM_IRQ_LEVEL) + SIU_VECT_BASE,
                  (void *)CpmIntrHandler, 0);

}