?? clock.bak
字號:
COORD (230,60)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#NAME="SetSel(2:0)"
#NUMBER="0"
}
LINE 2, 0, 0
{
POINTS ( (-20,0), (0,0) )
}
}
PIN 10, 0, 0
{
COORD (0,60)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="SetKey"
#NUMBER="0"
#SIDE="left"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 12, 0, 0
{
COORD (0,140)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="Clk100Hz"
#NUMBER="0"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
SYMBOL "#default" "StopWatch" "StopWatch"
{
HEADER
{
VARIABLES
{
#DESCRIPTION=""
#LANGUAGE="VERILOG"
#MODIFIED="1047651562"
}
}
PAGE ""
{
PAGEHEADER
{
RECT (0,0,300,240)
FREEID 32
}
BODY
{
RECT 1, -1, 0
{
VARIABLES
{
#OUTLINE_FILLING="1"
}
AREA (20,0,280,233)
}
TEXT 17, 0, 0
{
TEXT "$#NAME"
RECT (25,10,114,34)
ALIGN 4
MARGINS (1,1)
PARENT 16
}
TEXT 21, 0, 0
{
TEXT "$#NAME"
RECT (25,130,108,154)
ALIGN 4
MARGINS (1,1)
PARENT 20
}
TEXT 23, 0, 0
{
TEXT "$#NAME"
RECT (129,10,275,34)
ALIGN 6
MARGINS (1,1)
PARENT 22
}
TEXT 25, 0, 0
{
TEXT "$#NAME"
RECT (25,90,150,114)
ALIGN 4
MARGINS (1,1)
PARENT 24
}
TEXT 27, 0, 0
{
TEXT "$#NAME"
RECT (25,50,153,74)
ALIGN 4
MARGINS (1,1)
PARENT 26
}
TEXT 29, 0, 0
{
TEXT "$#NAME"
RECT (25,170,120,194)
ALIGN 4
MARGINS (1,1)
PARENT 28
}
TEXT 31, 0, 0
{
TEXT "$#NAME"
RECT (25,210,136,234)
ALIGN 4
MARGINS (1,1)
PARENT 30
}
PIN 16, 0, 0
{
COORD (0,20)
VARIABLES
{
#DIRECTION="IN"
#DOWNTO="1"
#LENGTH="20"
#NAME="Mode(1:0)"
#NUMBER="0"
#SIDE="left"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 20, 0, 0
{
COORD (0,140)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="GlbReset"
#NUMBER="0"
#SIDE="left"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 22, 0, 0
{
COORD (300,20)
VARIABLES
{
#DIRECTION="OUT"
#DOWNTO="1"
#LENGTH="20"
#NAME="StopWatch(31:0)"
#NUMBER="0"
#SIDE="right"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (-20,0) )
}
}
PIN 24, 0, 0
{
COORD (0,100)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="HoldResetKey"
#NUMBER="0"
#SIDE="left"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 26, 0, 0
{
COORD (0,60)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="StartPauseKey"
#NUMBER="0"
#SIDE="left"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 28, 0, 0
{
COORD (0,180)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="Clk4096Hz"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
PIN 30, 0, 0
{
COORD (0,220)
VARIABLES
{
#DIRECTION="IN"
#LENGTH="20"
#NAME="Clk100HzCE"
#NUMBER="0"
#SIDE="left"
#VERILOG_TYPE="wire"
}
LINE 2, 0, 0
{
POINTS ( (0,0), (20,0) )
}
}
}
}
}
}
PAGE ""
{
PAGEHEADER
{
PAGESIZE (3307,2338)
MARGINS (200,200,200,200)
RECT (0,0,100,200)
}
BODY
{
INSTANCE 21, 0, 0
{
VARIABLES
{
#COMMENT="鬧鐘設定模塊"
#COMPONENT="AlarmSet"
#LIBRARY="#default"
#REFERENCE="UAlarmSet"
#SYMBOL="AlarmSet"
}
COORD (1310,1470)
VERTEXES ( (2,10895), (4,11605), (6,10897), (8,11607), (10,10899), (12,10911), (14,10901), (16,10904), (18,10962), (20,10913), (22,12483) )
}
TEXT 22, 0, 0
{
TEXT "$#REFERENCE"
RECT (1310,1414,1453,1449)
ALIGN 8
MARGINS (1,1)
PARENT 21
}
TEXT 26, 0, 0
{
TEXT "$#COMPONENT"
RECT (1310,1730,1432,1765)
MARGINS (1,1)
PARENT 21
}
INSTANCE 30, 0, 0
{
VARIABLES
{
#COMMENT="鬧鐘輸出控制模塊"
#COMPONENT="Alarm"
#LIBRARY="#default"
#REFERENCE="U_Alarm"
#SYMBOL="Alarm"
}
COORD (2230,1470)
VERTEXES ( (2,11606), (6,11608), (8,11609), (10,11628), (12,11631), (14,11634), (20,11616), (26,11624), (28,11646), (30,11679), (32,11683), (34,11695) )
}
TEXT 31, 0, 0
{
TEXT "$#REFERENCE"
RECT (2230,1414,2346,1449)
ALIGN 8
MARGINS (1,1)
PARENT 30
}
TEXT 35, 0, 0
{
TEXT "$#COMPONENT"
RECT (2230,1950,2309,1985)
MARGINS (1,1)
PARENT 30
}
INSTANCE 57, 0, 0
{
VARIABLES
{
#COMMENT="模式切換主控模塊"
#COMPONENT="MainControl"
#LIBRARY="#default"
#REFERENCE="UMode"
#SYMBOL="MainControl"
}
COORD (1170,330)
VERTEXES ( (4,11449), (6,11459), (8,11455), (12,11891), (2,12461), (10,12457) )
}
TEXT 58, 0, 0
{
TEXT "$#REFERENCE"
RECT (1170,274,1264,309)
ALIGN 8
MARGINS (1,1)
PARENT 57
}
TEXT 62, 0, 0
{
TEXT "$#COMPONENT"
RECT (1170,530,1328,565)
MARGINS (1,1)
PARENT 57
}
INSTANCE 66, 0, 0
{
VARIABLES
{
#COMMENT="數碼管顯示控制模塊"
#COMPONENT="DispControl"
#LIBRARY="#default"
#REFERENCE="U_DispConctrol"
#SYMBOL="DispControl"
}
COORD (2390,320)
VERTEXES ( (2,11810), (6,11822), (18,11247), (22,11255), (24,11028), (36,11257), (38,11030), (44,11243), (46,11032), (50,11251), (52,11249), (54,11261), (56,11818), (58,11814), (60,11334), (62,11794), (64,11034), (66,11259), (68,11828), (72,11831), (78,11072), (80,11834), (86,12311) )
}
TEXT 67, 0, 0
{
TEXT "$#REFERENCE"
RECT (2390,264,2597,299)
ALIGN 8
MARGINS (1,1)
PARENT 66
}
TEXT 71, 0, 0
{
TEXT "$#COMPONENT"
RECT (2430,1180,2585,1215)
MARGINS (1,1)
PARENT 66
}
INSTANCE 75, 0, 0
{
VARIABLES
{
#COMMENT="秒表模塊"
#COMPONENT="StopWatch"
#LIBRARY="#default"
#REFERENCE="UStopWatch"
#SYMBOL="StopWatch"
}
COORD (1640,800)
VERTEXES ( (20,11331), (22,11335), (24,11329), (26,11327), (16,12172), (28,12174), (30,12178) )
}
TEXT 76, 0, 0
{
TEXT "$#REFERENCE"
RECT (1640,764,1807,799)
ALIGN 8
MARGINS (1,1)
PARENT 75
}
TEXT 80, 0, 0
{
TEXT "$#COMPONENT"
RECT (1640,1040,1786,1075)
MARGINS (1,1)
PARENT 75
}
NET WIRE 406, 0, 0
{
VARIABLES
{
#NAME="AlarmEn"
#VERILOG_TYPE="wire"
}
}
INSTANCE 459, 0, 0
{
VARIABLES
{
#COMPONENT="Output"
#LIBRARY="#terminals"
#REFERENCE="AlarmEn"
#SYMBOL="Output"
#VERILOG_TYPE="wire"
}
COORD (2880,1310)
VERTEXES ( (2,10955) )
}
TEXT 460, 0, 0
{
TEXT "$#REFERENCE"
RECT (2932,1293,3046,1328)
ALIGN 4
MARGINS (1,1)
PARENT 459
}
INSTANCE 474, 0, 0
{
VARIABLES
{
#COMPONENT="Output"
#LIBRARY="#terminals"
#REFERENCE="Buzzer"
#SYMBOL="Output"
#VERILOG_TYPE="wire"
}
COORD (2880,1490)
VERTEXES ( (2,11696) )
}
TEXT 475, 0, 0
{
TEXT "$#REFERENCE"
RECT (2932,1473,3023,1508)
ALIGN 4
MARGINS (1,1)
PARENT 474
}
NET WIRE 787, 0, 0
TEXT 807, 0, 0
{
TEXT "$#NAME"
RECT (2353,1271,2447,1300)
ALIGN 9
MARGINS (1,1)
PARENT 10960
}
NET BUS 944, 0, 0
{
VARIABLES
{
#NAME="Mode(1:0)"
#VERILOG_TYPE="wire"
}
}
TEXT 953, 0, 0
{
TEXT "$#NAME"
RECT (1460,321,1570,350)
ALIGN 9
MARGINS (1,1)
PARENT 11452
}
TEXT 985, 0, 0
{
TEXT "$#NAME"
RECT (1172,1460,1282,1489)
ALIGN 9
MARGINS (1,1)
PARENT 10926
}
TEXT 1016, 0, 0
{
TEXT "$#NAME"
RECT (1168,1500,1290,1529)
ALIGN 9
MARGINS (1,1)
PARENT 10928
}
NET WIRE 1088, 0, 0
{
VARIABLES
{
#NAME="GlbReset"
#VERILOG_TYPE="wire"
}
}
TEXT 1089, 0, 0
{
TEXT "$#NAME"
RECT (1180,1580,1283,1609)
ALIGN 9
MARGINS (1,1)
PARENT 10927
}
INSTANCE 1126, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="Clk2"
#SYMBOL="Input"
#VERILOG_TYPE="wire"
}
COORD (310,900)
VERTEXES ( (2,12033) )
}
TEXT 1127, 0, 0
{
TEXT "$#REFERENCE"
RECT (199,883,259,918)
ALIGN 6
MARGINS (1,1)
PARENT 1126
}
INSTANCE 1131, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="Key3"
#SYMBOL="Input"
#VERILOG_TYPE="wire"
}
COORD (320,430)
VERTEXES ( (2,11386) )
}
TEXT 1132, 0, 0
{
TEXT "$#REFERENCE"
RECT (203,413,269,448)
ALIGN 6
MARGINS (1,1)
PARENT 1131
}
INSTANCE 1136, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="Key2"
#SYMBOL="Input"
#VERILOG_TYPE="wire"
}
COORD (320,390)
VERTEXES ( (2,11388) )
}
TEXT 1137, 0, 0
{
TEXT "$#REFERENCE"
RECT (203,373,269,408)
ALIGN 6
MARGINS (1,1)
PARENT 1136
}
INSTANCE 1141, 0, 0
{
VARIABLES
{
#COMPONENT="Input"
#LIBRARY="#terminals"
#REFERENCE="Key1"
#SYMBOL="Input"
#VERILOG_TYPE="wire"
}
COORD (320,350)
VERTEXES ( (2,11390) )
}
TEXT 1142, 0, 0
{
TEXT "$#REFERENCE"
RECT (203,333,269,368)
ALIGN 6
MARGINS (1,1)
PARENT 1141
}
NET WIRE 1739, 0, 0
{
VARIABLES
{
#NAME="SetCP"
}
}
TEXT 1748, 0, 0
{
TEXT "$#NAME"
RECT (1200,1540,1271,1569)
ALIGN 9
MARGINS (1,1)
PARENT 10925
}
TEXT 1780, 0, 0
{
TEXT "$#NAME"
RECT (1459,911,1562,940)
ALIGN 9
MARGINS (1,1)
PARENT 11339
}
TEXT 1788, 0, 0
{
TEXT "$#NAME"
RECT (1463,861,1618,890)
ALIGN 9
MARGINS (1,1)
PARENT 11338
}
NET WIRE 2282, 0, 0
{
VARIABLES
{
#NAME="ModeKey"
}
}
TEXT 2283, 0, 0
{
TEXT "$#NAME"
RECT (920,321,1022,350)
ALIGN 9
MARGINS (1,1)
PARENT 12470
}
TEXT 2375, 0, 0
{
TEXT "$#NAME"
RECT (1079,401,1182,430)
ALIGN 9
MARGINS (1,1)
PARENT 11461
}
NET WIRE 2445, 0, 0
{
VARIABLES
{
#NAME="Clk8Hz"
}
}
NET WIRE 2454, 0, 0
{
VARIABLES
{
#NAME="Clk4096Hz"
}
}
TEXT 2455, 0, 0
{
TEXT "$#NAME"
RECT (301,871,419,900)
ALIGN 9
MARGINS (1,1)
PARENT 12037
}
TEXT 2774, 0, 0
{
TEXT "$#NAME"
RECT (439,950,542,979)
ALIGN 9
MARGINS (1,1)
PARENT 12038
}
TEXT 2876, 0, 0
{
TEXT "$#NAME"
RECT (1997,1620,2100,1649)
ALIGN 9
MARGINS (1,1)
PARENT 11630
}
TEXT 2880, 0, 0
{
TEXT "$#NAME"
RECT (2013,1660,2102,1689)
ALIGN 9
MARGINS (1,1)
PARENT 11633
}
TEXT 2884, 0, 0
{
TEXT "$#NAME"
RECT (2012,1700,2104,1729)
ALIGN 9
MARGINS (1,1)
PARENT 11636
}
TEXT 2896, 0, 0
{
TEXT "$#NAME"
RECT (1672,1461,1766,1490)
ALIGN 9
MARGINS (1,1)
PARENT 10958
}
NET WIRE 3167, 0, 0
{
VARIABLES
{
#NAME="SetKey"
}
}
TEXT 3168, 0, 0
{
TEXT "$#NAME"
RECT (924,360,1038,389)
ALIGN 9
MARGINS (1,1)
PARENT 12468
}
NET WIRE 3180, 0, 0
{
VARIABLES
{
#NAME="SetSelKey"
}
}
TEXT 3204, 0, 0
{
TEXT "$#NAME"
RECT (1469,831,1631,860)
ALIGN 9
MARGINS (1,1)
PARENT 11337
}
NET WIRE 3711, 0, 0
{
VARIABLES
{
#NAME="Clk1Hz"
}
}
TEXT 3818, 0, 0
{
TEXT "$#NAME"
RECT (1459,361,1581,390)
ALIGN 9
MARGINS (1,1)
PARENT 11458
}
NET WIRE 4249, 0, 0
{
VARIABLES
{
#NAME="AAM"
}
}
TEXT 4269, 0, 0
{
TEXT "$#NAME"
RECT (1625,1691,1676,1720)
ALIGN 9
MARGINS (1,1)
PARENT 10932
}
INSTANCE 4429, 0, 0
{
VARIABLES
{
#COMMENT="時鐘/日歷模塊"
#COMPONENT="ClockCalendar"
#LIBRARY="#default"
#REFERENCE="U_Clock_Calendar"
#SYMBOL="ClockCalendar"
}
COORD (1630,290)
VERTEXES ( (4,11244), (6,11447), (8,11248), (10,11788), (12,11250), (14,11785), (16,11252), (18,11453), (20,11256), (22,11258), (24,11260), (26,11262), (28,12414), (30,12513) )
}
TEXT 4430, 0, 0
{
TEXT "$#REFERENCE"
RECT (1630,234,1876,269)
ALIGN 8
MARGINS (1,1)
PARENT 4429
}
TEXT 4434, 0, 0
{
TEXT "$#COMPONENT"
RECT (1630,630,1823,665)
MARGINS (1,1)
PARENT 4429
}
NET BUS 4521, 0, 0
{
VARIABLES
{
#NAME="SetSel(2:0)"
#VERILOG_TYPE="wire"
}
}
TEXT 5028, 0, 0
{
TEXT "$#NAME"
RECT (1578,1620,1722,1649)
ALIGN 9
MARGINS (1,1)
PARENT 10964
}
TEXT 5242, 0, 0
{
TEXT "$#NAME"
RECT (1527,400,1598,429)
ALIGN 9
MARGINS (1,1)
PARENT 11787
}
TEXT 5246, 0, 0
{
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