SCHM0102

HEADER
{
 FREEID 1514
 VARIABLES
 {
  #BLOCKTABLE_FILE="#table.bde"
  #BLOCKTABLE_INCLUDED="1"
  #LANGUAGE="VERILOG"
  #MODULE="StopWatchCount"
  AUTHOR="zjj"
  COMPANY="hust"
  CREATIONDATE="2003-03-14"
  TITLE="No Title"
 }
 SYMBOL "#default" "BCD2Count" "BCD2Count"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #GENERIC0="Size:integer:=7"
    #GENERIC1="Begin:integer:=0"
    #GENERIC2="End:integer:='h59"
    #LANGUAGE="VERILOG"
    #MODIFIED="1047645490"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,0,280,100)
    FREEID 10
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,260,80)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,50,54,74)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (121,10,255,34)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (131,48,160,72)
     ALIGN 6
     MARGINS (1,1)
     PARENT 6
     ORIENTATION 4
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,10,78,34)
     ALIGN 4
     MARGINS (1,1)
     PARENT 8
    }
    PIN  2, 0, 0
    {
     COORD (0,60)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="CE"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (280,20)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="Count(Size-1:0)"
      #NUMBER="0"
      #SIDE="right"
      #VERILOG_TYPE="reg"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (140,100)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Clk"
      #NUMBER="0"
      #SIDE="bottom"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,-20) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (0,20)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Reset"
      #NUMBER="0"
      #SIDE="left"
      #VERILOG_TYPE="wire"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
 SYMBOL "myveriloglib" "BCD2CountTC" "BCD2CountTC"
 {
  HEADER
  {
   VARIABLES
   {
    #DESCRIPTION=""
    #GENERIC0="Size:integer:=7"
    #GENERIC1="Begin:integer:=0"
    #GENERIC2="End:integer:='h59"
    #LANGUAGE="VERILOG"
    #MODIFIED="1048591733"
   }
  }
  PAGE "" 
  {
   PAGEHEADER
   {
    RECT (0,-20,280,100)
    FREEID 12
   }
   
   BODY
   {
    RECT  1, -1, 0
    {
     VARIABLES
     {
      #OUTLINE_FILLING="1"
     }
     AREA (20,0,260,80)
    }
    TEXT  3, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,50,54,74)
     ALIGN 4
     MARGINS (1,1)
     PARENT 2
    }
    TEXT  5, 0, 0
    {
     TEXT "$#NAME"
     RECT (121,10,255,34)
     ALIGN 6
     MARGINS (1,1)
     PARENT 4
    }
    TEXT  7, 0, 0
    {
     TEXT "$#NAME"
     RECT (126,46,155,70)
     ALIGN 6
     MARGINS (1,1)
     PARENT 6
     ORIENTATION 4
    }
    TEXT  9, 0, 0
    {
     TEXT "$#NAME"
     RECT (227,50,255,74)
     ALIGN 6
     MARGINS (1,1)
     PARENT 8
    }
    TEXT  11, 0, 0
    {
     TEXT "$#NAME"
     RECT (25,10,78,34)
     ALIGN 4
     MARGINS (1,1)
     PARENT 10
    }
    PIN  2, 0, 0
    {
     COORD (0,60)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="CE"
      #NUMBER="0"
      #SIDE="left"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
    PIN  4, 0, 0
    {
     COORD (280,20)
     VARIABLES
     {
      #DIRECTION="OUT"
      #DOWNTO="1"
      #LENGTH="20"
      #NAME="Count(Size-1:0)"
      #NUMBER="0"
      #SIDE="right"
      #VERILOG_TYPE="reg"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  6, 0, 0
    {
     COORD (140,100)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Clk"
      #NUMBER="0"
      #SIDE="bottom"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (0,-20) )
     }
    }
    PIN  8, 0, 0
    {
     COORD (280,60)
     VARIABLES
     {
      #DIRECTION="OUT"
      #LENGTH="20"
      #NAME="TC"
      #NUMBER="0"
      #SIDE="right"
     }
     LINE  2, 0, 0
     {
      POINTS ( (-20,0), (0,0) )
     }
    }
    PIN  10, 0, 0
    {
     COORD (0,20)
     VARIABLES
     {
      #DIRECTION="IN"
      #LENGTH="20"
      #NAME="Reset"
      #NUMBER="0"
      #SIDE="left"
     }
     LINE  2, 0, 0
     {
      POINTS ( (0,0), (20,0) )
     }
    }
   }
  }
 }
}

PAGE ""
{
 PAGEHEADER
 {
  PAGESIZE (3307,2338)
  MARGINS (200,200,200,200)
  RECT (0,0,100,200)
 }
 
 BODY
 {
  INSTANCE  152, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BCD2CountTC"
    #GENERIC0="Begin : integer := 0"
    #GENERIC1="End : integer := 8'h99"
    #GENERIC2="Size : integer := 8"
    #LIBRARY="myveriloglib"
    #REFERENCE="U_PerSec"
    #SYMBOL="BCD2CountTC"
   }
   COORD (530,530)
   VERTEXES ( (2,728), (4,1112), (6,769), (8,1297) )
  }
  TEXT  153, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (530,474,664,509)
   ALIGN 8
   MARGINS (1,1)
   PARENT 152
  }
  TEXT  157, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (530,630,726,665)
   MARGINS (1,1)
   PARENT 152
  }
  INSTANCE  161, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BCD2Count"
    #GENERIC0="Begin : integer := 0"
    #GENERIC1="End : integer := 'h23"
    #GENERIC2="Size : integer := 6"
    #LIBRARY="#default"
    #REFERENCE="U_Hour"
    #SYMBOL="BCD2Count"
   }
   COORD (2520,530)
   VERTEXES ( (4,1107), (6,1256), (2,1367) )
  }
  TEXT  162, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2520,494,2622,529)
   ALIGN 8
   MARGINS (1,1)
   PARENT 161
  }
  TEXT  166, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (2660,640,2816,675)
   MARGINS (1,1)
   PARENT 161
  }
  INSTANCE  170, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BCD2CountTC"
    #GENERIC0="Begin : integer := 0"
    #GENERIC1="End : integer := 7'h59"
    #GENERIC2="Size : integer := 7"
    #LIBRARY="myveriloglib"
    #REFERENCE="U_Sec"
    #SYMBOL="BCD2CountTC"
   }
   COORD (1120,530)
   VERTEXES ( (2,1166), (4,1114), (6,1023), (8,1284) )
  }
  TEXT  171, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1120,474,1209,509)
   ALIGN 8
   MARGINS (1,1)
   PARENT 170
  }
  TEXT  172, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1170,630,1366,665)
   MARGINS (1,1)
   PARENT 170
  }
  INSTANCE  173, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BCD2CountTC"
    #GENERIC0="Size : integer := 7"
    #GENERIC1="Begin : integer := 0"
    #GENERIC2="End : integer := 7'59"
    #LIBRARY="myveriloglib"
    #REFERENCE="U_Min"
    #SYMBOL="BCD2CountTC"
   }
   COORD (1790,530)
   VERTEXES ( (2,1261), (4,1105), (6,1071), (8,1356) )
  }
  TEXT  174, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1790,474,1875,509)
   ALIGN 8
   MARGINS (1,1)
   PARENT 173
  }
  TEXT  175, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1790,630,1986,665)
   MARGINS (1,1)
   PARENT 173
  }
  NET WIRE  178, 0, 0
  NET WIRE  182, 0, 0
  NET WIRE  186, 0, 0
  INSTANCE  244, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="SWPer(7:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2880,360)
   VERTEXES ( (2,1113) )
  }
  TEXT  245, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2932,343,3088,378)
   ALIGN 4
   MARGINS (1,1)
   PARENT 244
  }
  INSTANCE  249, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="SWSec(6:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2880,420)
   VERTEXES ( (2,1115) )
  }
  TEXT  250, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2932,403,3093,438)
   ALIGN 4
   MARGINS (1,1)
   PARENT 249
  }
  INSTANCE  254, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="SWMin(6:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2880,470)
   VERTEXES ( (2,1106) )
  }
  TEXT  255, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2932,453,3089,488)
   ALIGN 4
   MARGINS (1,1)
   PARENT 254
  }
  INSTANCE  259, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusOutput"
    #LIBRARY="#terminals"
    #REFERENCE="SWHour(5:0)"
    #SYMBOL="BusOutput"
    #VERILOG_TYPE="wire"
   }
   COORD (2880,550)
   VERTEXES ( (2,1108) )
  }
  TEXT  260, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2932,533,3106,568)
   ALIGN 4
   MARGINS (1,1)
   PARENT 259
  }
  INSTANCE  264, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Global"
    #LIBRARY="#connectors"
    #REFERENCE="Reset"
    #SYMBOL="Global"
    #VERILOG_TYPE="wire"
   }
   COORD (510,410)
  }
  TEXT  265, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (525,393,603,428)
   ALIGN 4
   MARGINS (1,1)
   PARENT 264
  }
  INSTANCE  273, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Reset"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (370,520)
   VERTEXES ( (2,491) )
  }
  TEXT  274, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (241,503,319,538)
   ALIGN 6
   MARGINS (1,1)
   PARENT 273
  }
  INSTANCE  278, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Clk"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (370,710)
   VERTEXES ( (2,651) )
  }
  TEXT  279, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (275,693,319,728)
   ALIGN 6
   MARGINS (1,1)
   PARENT 278
  }
  INSTANCE  283, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="CE"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (370,590)
   VERTEXES ( (2,727) )
  }
  TEXT  284, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (277,573,319,608)
   ALIGN 6
   MARGINS (1,1)
   PARENT 283
  }
  NET WIRE  327, 0, 0
  NET WIRE  330, 0, 0
  NET BUS  334, 0, 0
  NET BUS  342, 0, 0
  NET BUS  367, 0, 0
  NET BUS  375, 0, 0
  VTX  491, 0, 0
  {
   COORD (370,520)
  }
  VTX  492, 0, 0
  {
   COORD (420,520)
  }
  WIRE  514, 0, 0
  {
   NET 330
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  {
   COORD (370,710)
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  VTX  727, 0, 0
  {
   COORD (370,590)
  }
  VTX  728, 0, 0
  {
   COORD (530,590)
  }
  VTX  769, 0, 0
  {
   COORD (670,630)
  }
  VTX  770, 0, 0
  {
   COORD (670,710)
  }
  WIRE  772, 0, 0
  {
   NET 327
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  }
  WIRE  773, 0, 0
  {
   NET 327
   VTX 651, 770
  }
  INSTANCE  984, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="and2"
    #LIBRARY="#builtin"
    #REFERENCE="U1"
    #SYMBOL="and2"
   }
   COORD (880,620)
   VERTEXES ( (6,1298), (2,1295), (4,1296) )
  }
  VTX  986, 0, 0
  {
   COORD (450,590)
  }
  WIRE  987, 0, 0
  {
   NET 993
   VTX 727, 986