// THIS FILE "const.h" was writen for the Quasar 3 + 3.5 // chip generation. // As Q3.5 became obsolete and Q4 was implemented the new // file used is Q4.h// The goal is to transfer all necesary definitions to Q4.h and// only use that file in the future.#define RBUS_reset_run					0x1000//---------------------------------------------------//------ DRAM Controller control registers ---------//---------------------------------------------------#define DRAM_config						0xC00#define DRAM_fifosize0					0xC01 #define DRAM_fifosize1					0xC02 #define DRAM_pllcontrol					0xC04 #define DRAM_ac3_base					0xC0A#define DRAM_fifosize2					0xC0B#define DRAM_portmux					0xC0C  //---BASE ADDRESSES OF DRAM CHANNELS--------------#define HOST_TO_DRAM_base				0xC10#define RISC_TO_DRAM_base				0xC20#define DRAM_TO_HOST_base				0xC50#define DRAM_TO_RISC_base				0xC60#define DRAM_TO_HD_base					0xC70#define MC_TO_DRAM_base					0xC80#define Display_Luma_base				0xC90#define Display_Chroma_base				0xCA0#define DRAM_TO_SPUTop_base				0xCB0#define DRAM_TO_SPUBot_base				0xCC0#define DRAM_TO_SPUCom_base				0xCD0#define DRAM_TO_SPDIF_base  			0xCE0#define W0_CNTR       					0xC10  #define W0_ADDD_L0						0xC11#define W0_ADDD_HI						0xC12#define W0_XCNT							0xC13#define W0_XCNT_RELOAD					0xC14#define W0_XCNT_SKIP					0xC15#define W0_YCNT							0xC16#define W0_YCNT_RELOAD					0xC17#define W0_ADD_RELOAD_LO				0xC18#define W0_ADD_RELOAD_HI				0xC19#define W0_ZCNT							0xC1A//---DRAM control register offsets Type 0-------------#define control0	0				//(R/W)#define addlo0		1               //(R/W)#define addhi0		2               //(R/W)#define xcnt0		3               //(R/W)#define xcnt_rld0	4               //(R/W)#define xskip0		5               //(R/W)#define ycnt0		6               //(R/W)#define ycnt_rld0	7               //(R/W)#define add_rld_lo0	8               //(R/W)#define add_rld_hi0	9               //(R/W)#define zcnt0		0xA             //(R/W)//---DRAM control register offsets Type 1-------------#define control1	0				//(R/W)#define addlo1		1 				//(R/W)#define addhi1		2               //(R/W)#define xcnt1		3               //(R/W)#define xcnt_rld1	4               //(R/W)#define add_rld_lo1	8               //(R/W)#define add_rld_hi1	9               //(R/W)#define zcnt1		0xA             //(R/W)//---DRAM control register offsets Type 2-------------#define control2	0				//(R/W)#define addlo2		1 				//(R)#define addhi2		2               //(R)#define xcnt2		3               //(R)#define xcnt_rld2	4               //(R)#define xskip2		5               //(R)#define ycnt2		6               //(R)#define zcnt2		0xA             //(R)//----- RISC(MISC) to DRAM transfer control registers// (Channel W1)#define write_DRAM_control				0xC20   // r/w#define write_DRAM_addlo				0xC21   // R/W#define write_DRAM_addhi				0xC22   // R/W#define write_DRAM_xcnt					0xC23   // R/W#define write_DRAM_xcnt_rld				0xC24   // R/W#define write_DRAM_xskip				0xC25   // R/W#define write_DRAM_ycnt					0xC26   // R/W#define write_DRAM_ycnt_rld				0xC27   // R/W#define write_DRAM_add_rld_lo			0xC28   // R/W#define write_DRAM_add_rld_hi			0xC29   // R/W#define write_DRAM_zcnt					0xC2A   // R/W#define W3_CNTR       					0xC40  #define W3_ADDD_L0						0xC41#define W3_ADDD_HI						0xC42#define W3_XCNT							0xC43#define W3_XCNT_RELOAD					0xC44#define W3_YCNT							0xC46#define W3_YCNT_RELOAD					0xC47#define W3_ZCNT							0xC4A#define R0_CNTR       					0xC50  #define R0_ADDD_L0						0xC51#define R0_ADDD_HI						0xC52#define R0_XCNT							0xC53#define R0_XCNT_RELOAD					0xC54#define R0_YCNT							0xC56#define R0_YCNT_RELOAD					0xC57#define R0_ZCNT							0xC5A// (Channel R1)#define read_DRAM_control				0xC60   // r/w#define read_DRAM_addlo					0xC61   // R/W#define read_DRAM_addhi					0xC62   // R/W#define read_DRAM_xcnt					0xC63   // R/W#define read_DRAM_xcnt_rld				0xC64   // R/W#define read_DRAM_xskip					0xC65   // R/W#define read_DRAM_ycnt					0xC66   // R/W#define read_DRAM_ycnt_rld				0xC67   // R/W#define read_DRAM_add_rld_lo			0xC68   // R/W#define read_DRAM_add_rld_hi			0xC69   // R/W#define read_DRAM_zcnt					0xC6A   // R/W//------ DRAM to Huffman Decoder transfer control registers// (Channel R2)	- HD FIFO control#define HDF_control						0xC70   // r/w#define HDF_addlo						0xC71   // R/W#define HDF_addhi						0xC72   // R/W#define HcDF_length						0xC73   // R/W#define HDF_length_rld					0xC74   // R/W#define HDF_add_rld_lo					0xC78   // R/W#define HDF_add_rld_hi					0xC79   // R/W#define HDF_transfer_cnt				0xC7A   // R/W//-- SPDIF serial interface -------------------------// (Channel R9)#define SPDIF_SERIAL_R9_control			0xCE0   // r/w#define SPDIF_SERIAL_R9_addlo			0xCE1   // R/W#define SPDIF_SERIAL_R9_addhi			0xCE2   // R/W#define SPDIF_SERIAL_R9_xcnt			0xCE3   // R/W#define SPDIF_SERIAL_R9_xcnt_rld		0xCE4   // R/W#define SPDIF_SERIAL_R9_xskip			0xCE5   // R/W#define SPDIF_SERIAL_R9_ycnt			0xCE6   // R/W#define SPDIF_SERIAL_R9_ycnt_rld		0xCE7   // R/W#define SPDIF_SERIAL_R9_add_rld_lo		0xCE8   // R/W#define SPDIF_SERIAL_R9_add_rld_hi		0xCE9   // R/W#define SPDIF_SERIAL_R9_zcnt			0xCEA   // R/W//-----  HOST WRITE 2 -------------------------------// (Channel W4)#define HOST_DRAM_2_control				0xCF0   // r/w#define HOST_DRAM_2_addlo				0xCF1   // R/W#define HOST_DRAM_2_addhi				0xCF2   // R/W#define HOST_DRAM_2_xcnt				0xCF3   // R/W#define HOST_DRAM_2_xcnt_rld			0xCF4   // R/W#define HOST_DRAM_2_xskip				0xCF5   // R/W#define HOST_DRAM_2_ycnt				0xCF6   // R/W#define HOST_DRAM_2_ycnt_rld			0xCF7   // R/W#define HOST_DRAM_2_add_rld_lo			0xCF8   // R/W#define HOST_DRAM_2_add_rld_hi			0xCF9   // R/W#define HOST_DRAM_2_zcnt				0xCFA   // R/W#define W4_CNTR       					0xCF0  #define W4_ADDD_L0						0xCF1#define W4_ADDD_HI						0xCF2#define W4_XCNT							0xCF3#define W4_XCNT_RELOAD					0xCF4#define W4_YCNT							0xCF6#define W4_YCNT_RELOAD					0xCF7#define W4_ZCNT							0xCFA//-- J1 -> DRAM   -------------------------// (Channel W5)#define AC3_W5_control					0xD00   // r/w#define AC3_W5_addlo					0xD01   // R/W#define AC3_W5_addhi					0xD02   // R/W#define AC3_W5_R9_xcnt					0xD03   // R/W#define AC3_W5_xcnt_rld					0xD04   // R/W#define AC3_W5_xskip					0xD05   // R/W#define AC3_W5_ycnt						0xD06   // R/W#define AC3_W5_ycnt_rld					0xD07   // R/W#define AC3_W5_add_rld_lo				0xD08   // R/W#define AC3_W5_add_rld_hi				0xD09   // R/W#define AC3_W5_zcnt						0xD0A   // R/W	//-- DRAM -> J1  -------------------------// (Channel R10)#define AC3_R10_control					0xD10   // r/w#define AC3_R10_addlo					0xD11   // R/W#define AC3_R10_addhi					0xD12   // R/W#define AC3_R10_xcnt					0xD13   // R/W#define AC3_R10_xcnt_rld				0xD14   // R/W#define AC3_R10_xskip					0xD15   // R/W#define AC3_R10_ycnt					0xD16   // R/W#define AC3_R10_ycnt_rld				0xD17   // R/W#define AC3_R10_add_rld_lo				0xD18   // R/W#define AC3_R10_add_rld_hi				0xD19   // R/W#define AC3_R10_zcnt					0xD1A   // R/W#define R11_CNTR       					0xD20  #define R11_ADDD_L0						0xD21#define R11_ADDD_HI						0xD22#define R11_XCNT						0xD23#define R11_XCNT_RELOAD					0xD24#define R11_YCNT						0xD26#define R11_ZCNT						0xD2A//---------------------------------------------------//-----  Local BUS LBC  -----------------------------//---------------------------------------------------#define LBC_config						0xE40#define LBC_config1						0xE41#define LBC_write_fifo0_access          0xE42#define LBC_write_fifo0_cnt             0xE43#define LBC_read_fifo0_access           0xE44#define LBC_read_fifo0_cnt              0xE45#define LBC_read_fifo1_access           0xE46#define LBC_read_fifo1_cnt              0xE47#define LBC_write_reg_addr              0xE48#define LBC_write_reg_data              0xE49#define LBC_read_reg_addr               0xE4A#define LBC_read_reg_data               0xE4B#define LBC_burst_xfer_ctrl             0xE4C#define LBC_status_reg                  0xE4D#define LBC_interrupt_reg               0xE4E#define LBC_PGIO_reg                    0xE4F//---------------------------------------------------//-----  OSD DMA channel			DBUS ADR//---------------------------------------------------#define OSD_source_rd_lo				0xE60#define OSD_source_rd_hi				0xE61																#define OSD_source_rd_counter			0xE62#define OSD_source_mux_en				0xE63#define OSD_rd_int_mask					0xE64#define OSD_rd_int						0xE65#define OSD_rd_int_status				0xE66//---------------------------------------------------//------ Huffman decoder registers -----------------//---------------------------------------------------#define HD_cmd							0xF00	// Write only#define HD_result						0xF01   // Read only#define HD_cntlo						0xF08   // R/W#define HD_cnthi						0xF09   // R/W//------ MC registers -----------------------------------#define MC_Base							0xF10#define YBASE0L0						0		// R/W#define YBASE0HI						1		// R/W#define CBASE0L0						2		// R/W#define CBASE0HI						3		// R/W#define YBASE1L0						4		// R/W#define YBASE1HI						5		// R/W#define CBASE1L0						6		// R/W#define CBASE1HI						7		// R/W#define YBASE2L0						8		// R/W#define YBASE2HI						9		// R/W#define CBASE2L0						0xA		// R/W#define CBASE2HI						0xB		// R/W#define PICSIZE							0xC		// R/W#define STRIDE							0xD		// R/W#define MC_cmd							0xE		// W#define MC_status						0xE		// R//--------Display Controller addresses-----------------                        #define VID_REG_BASE					0xf40#define VID_Y_BCS						0#define VID_C_BCS						1#define VID_HSYNC_LO					2#define VID_HSYNC_HI					3#define VID_VSYNC_LO					4#define VID_VSYNC_HI					5#define VID_VSYNC_DLY					6#define VID_SYNC_CTRL					7#define VID_Y_MPEGLINE					8#define VID_C_MPEGLINE					9#define VID_SCAN_LINE					0xA#define VID_SCAN_MAX					0xB//#define PIO_DATA          				0xD//#define PIO_DIR           				0xE#define VID_REG_BASE_2					0xf50#define VID_WIDTH						0x3#define VID_HEIGHT						0x4#define VID_DISCARD						0x5#define VID_HDS_SCALE					0x6#define VID_VUS_SCALE					0x7   #define VID_HUS_SCALE     				0x8#define VID_US_PHASE      				0x9#define VID_WIN_TOP       				0xA#define VID_WIN_BOT       				0xB#define VID_WIN_LEFT      				0xC#define VID_WIN_RIGHT     				0xD#define VID_CTRL          				0xE#define VID_IRQ           				0xF//------- Sub picture module registers------------------------------#define SP_REG_BASE						0xf60#define SP_COLOR						0#define SP_CONTRAST						1#define SP_HOFFSET						2#define SP_VOFFSET						3#define SP_WIDTH						4#define SP_HEIGHT						5#define SP_HCROP_WIDTH					6#define SP_VDS_SCALE					7#define SP_HDS_SCALE					8#define SP_VUS_SCALE					9#define SP_HUS_SCALE					10#define SP_WIN_TOP						11#define SP_WIN_BOT						12#define SP_WIN_LEFT						13#define SP_WIN_RIGHT					14#define SP_CTRL							15#define SP_REG_BASE_2					0xf70#define BTN_COLOR          				0#define BTN_CONTR          				1#define BTN_WIN_TOP        				2#define BTN_WIN_BOT        				3#define BTN_WIN_LEFT       				4#define BTN_WIN_RIGHT      				5                             #define SP_CLUT_BASE					0xf80#define SP_CLUT_Y0						0x0#define SP_CLUT_C0						0x1#define SP_CLUT_Y1						0x2#define SP_CLUT_C1						0x3#define SP_CLUT_Y2						0x4#define SP_CLUT_C2						0x5#define SP_CLUT_Y3						0x6#define SP_CLUT_C3						0x7#define SP_CLUT_Y4						0x8#define SP_CLUT_C4						0x9#define SP_CLUT_Y5						0xA#define SP_CLUT_C5						0xB#define SP_CLUT_Y6						0xC#define SP_CLUT_C6						0xD#define SP_CLUT_Y7						0xE#define SP_CLUT_C7						0xF   #define SP_CLUT_BASE_2					0xf90#define SP_CLUT_Y8         				0x0#define SP_CLUT_C8						0x1#define SP_CLUT_Y9						0x2#define SP_CLUT_C9						0x3#define SP_CLUT_Y10						0x4#define SP_CLUT_C10						0x5#define SP_CLUT_Y11						0x6#define SP_CLUT_C11						0x7#define SP_CLUT_Y12						0x8#define SP_CLUT_C12						0x9#define SP_CLUT_Y13						0xA#define SP_CLUT_C13						0xB#define SP_CLUT_Y14						0xC#define SP_CLUT_C14						0xD#define SP_CLUT_Y15						0xE#define SP_CLUT_C15						0xF#define SP_CLUT_YC						0xf80