#define SP_CLUT_SIZE					32//---------------------------------------------------//-----  AUDIO/PCM    -------------------------------//---------------------------------------------------#define AUDIO_pcm_mix0					0xFB0   // R/W#define AUDIO_pcm_mix1					0xFB1   // R/W#define AUDIO_pcm_mix2					0xFB2   // R/W#define AUDIO_pcm_mix3					0xFB3   // R/W#define AUDIO_pcm_mix4					0xFB4   // R/W#define AUDIO_pcm_mix5					0xFB5   // R/W#define AUDIO_pcm_mix6					0xFB6   // R/W#define AUDIO_pcm_mix7					0xFB7   // R/W#define AUDIO_pcm_invert				0xFB8   // R/W#define AUDIO_pcm_config0				0xFB9   // R/W #define AUDIO_pcm_config1				0xFBA   // R/W //---------------------------------------------------//-----  AUDIO/AC3    -------------------------------//---------------------------------------------------#define AUDIO_ac3_status_lo				0xFC0   // R#define AUDIO_ac3_status_hi				0xFC1   // R#define AUDIO_ac3_cop					0xFC2   // R/W/A#define AUDIO_ac3_mode					0xFC3   // R/W#define AUDIO_ac3_romaddsel				0xFC4   // R/W #define AUDIO_ac3_romdatalo				0xFC5   // R/W#define AUDIO_ac3_romdatahi				0xFC6   // R/W//---------------------------------------------------//-----  AUDIO/SERIAL -------------------------------//---------------------------------------------------#define AUDIO_bytecnt_lo				0xFD0   // R/W #define AUDIO_bytecnt_hi				0xFD1   // R/W #define AUDIO_bytecnt_trig_lo			0xFD2   // R/W #define AUDIO_bytecnt_trig_hi			0xFD3   // R/W #define AUDIO_sync_state       			0xFD4   // R/W/A #define AUDIO_serial_ctrl0      		0xFD5   // R/W#define AUDIO_serial_ctrl1      		0xFD6   // R/W#define AUDIO_serial_gain       		0xFD7   // R/W#define AUDIO_spdif_ch_stat0    		0xFD8   // R/W#define AUDIO_spdif_ch_stat1    		0xFD9   // R/W#define AUDIO_in_counter        		0xFDB   // R/W//---------------------------------------------------//------ PCI Master					DBUS ADR//-----  H2Q DMA Registers			DBUS ADR//---------------------------------------------------#define PCI_Add_Lo						0xFE0#define PCI_Add_Hi						0xFE1#define PCI_DataCounter					0xFE2#define PCI_SecondaryMasterEnable		0xFE3#define PCI_DataOrder					0xFE4//---------------------------------------------------#define HOST_Add_Lo						0xFE0#define HOST_Add_Hi						0xFE1#define HOST_DataCounter				0xFE2#define HOST_SecondaryMasterEnable		0xFE3#define HOST_H2Q_int_mask				0xFE4#define HOST_H2Q_int					0xFE5#define HOST_H2Q_int_status				0xFE6//---------------------------------------------------//---------------------------------------------------//-----  QMP-DBUS Registers			DBUS ADR//-----  Q2H DMA Registers			DBUS ADR//---------------------------------------------------#define QMP_waddr_lo					0xFE8	// new in Quasar3.5#define QMP_waddr_hi					0xFE9	// new in Quasar3.5#define QMP_xfer_cnt					0xFEA	// new in Quasar3.5#define QMP_wmaster_ena					0xFEB	// new in Quasar3.5//---------------------------------------------------#define Q2H_wr_addr_lo					0xFE8#define Q2H_wr_addr_hi					0xFE9#define Q2H_wr_counter					0xFEA#define Q2H_wr_master_en				0xFEB#define Q2H_rd_int_mask					0xFEC#define Q2H_rd_int						0xFED#define Q2H_rd_int_status				0xFEE//---------------------------------------------------//------ RISCMISC block control registers ----------//---------------------------------------------------#define RISC_misc_base					0xff0#define RISC_mode_w						0		// 0xff0#define RISC_length_w					1		// 0xff1#define RISC_address_w					2		// 0xff2#define RISC_loopback					3		// 0xff3#define RISC_mode_r						4		// 0xff4#define RISC_length_r					5		// 0xff5#define RISC_address_r					6		// 0xff6#define RISC_resets_0					8		// 0xff8#define RISC_resets_1					9		// 0xff9#define RISC_irq						0xa		// 0xffa#define RISC_tim_div					0xb		// 0xffb#define RISC_tim_cnt					0xc		// 0xffc//---------------------------------------------------#define write_RAM_mode					0xFF0   // R/W	 (mode_w)#define write_RAM_length				0xFF1   // R/W	 (length_w)#define write_RAM_address				0xFF2   // R/W	 (address_w)#define RISC_DRAM_loopback				0xFF3   // R/W#define read_RAM_mode					0xFF4   // R/W	 (mode_r)#define read_RAM_length					0xFF5   // R/W	 (length_r)#define read_RAM_address				0xFF6   // R/W	 (address_r)#define RISCMISC_reserved				0xFF7	// reserved#define RISC_reset0						0xFF8#define RISC_reset1						0xFF9#define Q2H_RISC_INT_REG				0xFFA	//irq_control	#define	TIM_div							0xFFB	// timer division R/W#define TIM_count						0xFFC	// R#define TIM_irq_clr						0xFFC	// W//-*************************************************//------ Parser definition         -----------------//-*************************************************#define Parser0_ctrl					0xFF7#define Parser0_ptr						0xFFD#define Parser1_ptr						0xFFE #define Parser1_ctrl					0xFFF//---------------------------------------------------//--- CONSTANT / COMMAND DEFINITIONS			  ---//---------------------------------------------------//--- dram ctrl constant definitions------------#define	TIMING				0x7#define REFRESH_PEROID		127#define	DRSIZE							0x0	// SDRAM 2MB 16 bit data//#define	DRSIZE						0x1	// SDRAM 2MB 32 bit data#define DRAM_REFRESH					64#define DRAM_TIMING						0#define DRAM_FIFO0						0x5555#define DRAM_FIFO1						0x0555#define TrMaxSize			0x1000	// the maximum size of the transfer										// from the video bitstream buffer (4KBytes)#define BSizeMax			0x40	// the buffer maximum size x 0x10000 (4MBytes)#define typ_tmax			8		// the typical value of the time-window 									// allocated to each DRAM channel// Huffman FIFO watch values#define FIFOWATCH_IDLE      0#define FIFOWATCH_ARMED     1#define FIFOWATCH_2ND       2#define FIFOWATCH_UNDERFLOW 3// Huffman decoder reset masks#define HD_UNRESET_MASK 0x2000#define HD_RESET_MASK	0x2020// Motion compensation reset masks#define MC_UNRESET_MASK 0x4000#define MC_RESET_MASK	0x4040// MPEG engine (MC+IQZ+IDCT+HD) reset masks#define MPEG_UNRESET_MASK 0xE000#define MPEG_RESET_MASK	  0xE0E0// MC+IQZ+IDCT reset masks#define MCIDCT_UNRESET_MASK 0xC000#define MCIDCT_RESET_MASK	0xC0C0// RISCMISC reset masks#define RISCMISC_UNRESET_MASK 0x1800#define RISCMISC_RESET_MASK	  0x1818// set PCI interrupt #define set_PCIint		  3//------ Inverse quantizer matrices start address -------#define QZ_iqm			  0xE00#define QZ_niqm			  0xE20//------ PCI IRQ register -------------------------------#define SP_init			  0x201		  // stack pointer initial value#define	ThRes			  0xA		  // the resolution of the buffer threshold value //------ MC commands -----------------------------------#define FWD_16x16  		0x1c0	// load command#define FWD_TOP_FLD  	0x1c1	// load command#define FWD_BOTT_FLD  	0x1c2	// load command#define FWD_16x8U  		0x1c3	// load command#define FWD_16x8B  		0x1c4	// load command#define BWD_16x16  		0x9c0	// load command #define BWD_TOP_FLD  	0x9c1	// load command#define BWD_BOTT_FLD  	0x9c2	// load command#define BWD_16x8U  		0x9c3	// load command#define BWD_16x8B  		0x9c4	// load command#define STO_FRM  		0x5100	// store command#define STO_FLD  		0x5500	// store command#define MV_BuffStart_Lo	0x44 #define MV_BuffStart_Hi	0x45 #define MV_BuffSize_Lo	0x46 #define MV_BuffSize_Hi	0x47 #define MV_RdPtr_Lo	0x48 #define MV_RdPtr_Hi	0x49 #define MV_WrPtr_Lo	0x4b #define MV_WrPtr_Hi	0x4c 	//------- Error Codes -----------------------------------//-----------------// sequence header//-----------------#define	null_pic_size				1   #define	no_aspect_ratio				2#define	frame_rate_err    			3#define	frame_rate_ext_err			4#define markbit_err					5#define seq_no_ext					6#define seq_no_seqext				7#define unknown_PL					8#define unsupp_PL					9#define unsupp_chroma				10#define s_iqm_err					11#define s_niqm_err					12//----------------// picture header//----------------#define no_vec_info					13#define no_pic_type					14#define pic_no_ext  				15#define pic_no_picext  				16#define null_r_size  				17#define unknown_picstr				18#define p_iqm_err					19#define p_niqm_err					20#define ch_iqm_err					21#define ch_niqm_err					22#define wrong_slice_sc				23//--------------// slice header//--------------#define wrong_skip					24#define null_motion_type			25//------- Start Codes ------------------------------#define SEQUENCE_HEADER_CODE		0xB3#define GROUP_START_CODE			0xB8#define PICTURE_START_CODE			0x00#define EXTENSION_START_CODE		0xB5  #define USER_DATA_START_CODE		0xB2#define	SEQUENCE_END_CODE			0xB7#define END_OF_STREAM				0x1F0//------- Extension ID Codes ------------------------------#define PIC_COD_ID 					8#define SEQ_EXT_ID					1//------- MPEG2 constants ------------------------------#define MP_ML						0x48  #define CHROMA420       			1                                // SP Display Control Command Codes#define FSTA_DSP	0#define STA_DSP		1#define STP_DSP	2#define SET_COLOR	3#define SET_CONTR	4#define SET_DAREA	5#define SET_DSPXA	6#define CHG_COLCON	7#define CMD_END		0xff#define PM_DESTINATION_LOW      0x00#define PM_DESTINATION_HIGH     0x01//---------------------------------------------------//-----  Stream Machine constant  -------------------//---------------------------------------------------#define SM_HOST_COMMAND                 0x0002 #define SM_TX_FIFO                      0x0006#define SM_RC_FIFO                      0x0008#define SM_INT_EN_CONTROL               0x000A#define SM_INT_INFO                     0x000C#define SM_DMA_INFO1_REG                0x000E#define SM_DMA_INFO2_REG                0x0010#define SM_BT_CNT_REG                   0x0016#define SM_I2C_TRANSMIT                 0x0018#define SM_I2C_RECEIVE                  0x001A#define SM_UCODE_DOWN                   0x001C#define SM_VQ_SIZE_Lo                   0x0020#define SM_VQ_SIZE_Hi                   0x0022#define SM_DRAM_TRAN_FIFO               0x8000#define SM_MPEG_RC_FIFO                 0xC000      //---------------------------------------------------//-----  ERROR CODE  in DM[SM_ERROR]   --------------//---------------------------------------------------#define SM_WR_ADDR_REG_ERROR           0x00001#define SM_WR_DATA_REG_ERROR           0x00002#define SM_RD_ADDR_REG_ERROR           0x00003#define SM_RD_DATA_REG_ERROR           0x00004//---------------------------------------------------//-----  INT PENDING for READ ONLY      --------------//---------------------------------------------------#define INT0_PENDING                   0x0001 #define INT1_PENDING                   0x0002 #define INT2_PENDING                   0x0004 #define INT3_PENDING                   0x0008 //---------------------------------------------------//-----  LBC_status BITs               --------------//---------------------------------------------------#define LBC_status_RR                  0x0001 #define LBC_status_RW                  0x0002#define LBC_status_LWCH0               0x0004#define LBC_status_LRCH0               0x0008#define LBC_status_LRCH1               0x0010//---------------------------------------------------//-----  Kfir registers                --------------//---------------------------------------------------#define Kfir_DMA_BSM_BURST      96#define Kfir_DMA_BSM_BURST_END  97#define Kfir_DMA_VIB_BURST      98#define Kfir_DMA_VIB_BURST_END  99#define Kfir_DEV_INST           200#define Kfir_DATA_MSB           202 // FIFO WRITE MSB#define Kfir_VIB_FIFO           203 // FIFO READ LSB#define Kfir_AUDIO_MEM          204 // FIFO READ MSB#define Kfir_I960_MASTER        211#define Kfir_FILE_MODE          212#define Kfir_RESET_REGS         213 //D5#define Kfir_RESET_FIFO         214 //D6 #define Kfir_VIDEO_INTER_BURST  219#define Kfir_INTER_CNT          221 //DD#define Kfir_AUDIO_INT_ACK      228#define Kfir_AUDIO_FRAME_SIZE   229#define Kfir_VIDEO_INTER        234#define Kfir_DMA_MUX_INTER      236#define Kfir_DMA_VIB_INTER      237#define Kfir_EREADY             254 // FE#define Kfir_RECORD             255 // FF//**************************************************//******* IO related defines  **********************//**************************************************// Huffman decoder commands#define GET_SC			0x11#define BYTEALIGN		0x12#define GET_MB			0x31#define GET_MBAI        0x13#define GET_MBTYPE      0x13#define GET_CBP_CBPY    0x17#define GET_MV          0x18#define GET_DMV_MODB    0x19#define RESET_ERR       0x3F// Other Stuff#define MAX_WrRdPTR_ParserSize80H 0x7F