#ifndef _EM85XX_PBI_H#define _EM85XX_PBI_H#define PBI_TOP_IRQ             25#define PB_BASE                 0x00800000#define PB_TIMING0              ( (volatile unsigned int *) (PB_BASE + 0x800) )#define PB_TIMING1              ( (volatile unsigned int *) (PB_BASE + 0x804) )#define PB_TIMING2              ( (volatile unsigned int *) (PB_BASE + 0x808) )#define PB_TIMING3              ( (volatile unsigned int *) (PB_BASE + 0x80C) )#define PB_TIMING4              ( (volatile unsigned int *) (PB_BASE + 0x810) )#define PB_TIMING5              ( (volatile unsigned int *) (PB_BASE + 0x814) )#define PB_DEFAULT_TIMING       ( (volatile unsigned int *) (PB_BASE + 0x818) )#define PB_USE_TIMING0          ( (volatile unsigned int *) (PB_BASE + 0x81C) )#define PB_USE_TIMING1          ( (volatile unsigned int *) (PB_BASE + 0x820) )#define PB_USE_TIMING2          ( (volatile unsigned int *) (PB_BASE + 0x824) )#define PB_USE_TIMING3          ( (volatile unsigned int *) (PB_BASE + 0x828) )#define PB_USE_TIMING4          ( (volatile unsigned int *) (PB_BASE + 0x82C) )#define PB_USE_TIMING5          ( (volatile unsigned int *) (PB_BASE + 0x830) )#define PB_CS_CONFIG            ( (volatile unsigned int *) (PB_BASE + 0x834) )#define PB_AUTOMODE_STARTADDR   ( (volatile unsigned int *) (PB_BASE + 0x840) )#define PB_AUTOMODE_CTRL        ( (volatile unsigned int *) (PB_BASE + 0x844) )#define PB_SL_CTRL              ( (volatile unsigned int *) (PB_BASE + 0x9C0) )#define PB_SL_INT               ( (volatile unsigned int *) (PB_BASE + 0x9C4) )#define PB_SL_INTEN             ( (volatile unsigned int *) (PB_BASE + 0x9C8) )#define PB_SL_ADDR_REG          ( (volatile unsigned int *) (PB_BASE + 0x9CC) )#define PB_SL_DIN_REG           ( (volatile unsigned int *) (PB_BASE + 0x9D0) )#define PB_SL_DOUT_REG          ( (volatile unsigned int *) (PB_BASE + 0x9D4) )#define PB_EXT_DEV1_REG_BASE    ( (volatile unsigned int *) (PB_BASE + 0x000) )#define PB_EXT_DEV2_REG_BASE    ( (volatile unsigned int *) (PB_BASE + 0x200) )#define PB_EXT_DEV3_REG_BASE    ( (volatile unsigned int *) (PB_BASE + 0x400) )#define PB_EXT_DEV4_REG_BASE    ( (volatile unsigned int *) (PB_BASE + 0x600) )#define PB_EXT_DEV1_MEM_BASE    ( (volatile unsigned int *) (0x10000000) )#define PB_EXT_DEV2_MEM_BASE    ( (volatile unsigned int *) (0x12000000) )#define PB_EXT_DEV3_MEM_BASE    ( (volatile unsigned int *) (0x18000000) )#define PB_EXT_DEV4_MEM_BASE    ( (volatile unsigned int *) (0x1A000000) )// Setting for TIMING#define PBI_TMASK_CS0           0x001#define PBI_TMASK_CS1           0x002#define PBI_TMASK_CS2           0x004#define PBI_TMASK_CS3           0x008#define PBI_TMASK_WR            0x010#define PBI_TMASK_RD            0x020#define PBI_TMASK_IDE           0x040#define PBI_TMASK_NONIDE        0x080#define PBI_TMASK_PIO           0x100#define PBI_TMASK_DMA           0x200// Setting for PB_CS_Config (for DEVICE 1, left shift for DEVICE 2,3,4)#define PBI_8BIT                0x0001#define PBI_PACKED              0x0010#define PBI_MUXAD               0x0100#define PBI_IDE                 0x1000#define PBI_JL                  0x10000         // no shifting// Setting for PBI register PB_SL_CTRL#define PBI_IN_LBC_PADS         0x1#define PBI_SLAVE_INTERFACE     0x2#define PBI_REMOVE_TRISTATE     0x4#define PBI_IN_IDE_PADS         0x8// Setting for PBI automode register// for PB_AUTOMODE_STARTADDR#define PBI_AM_AUTO_INCREMENT   0x01000000// for PB_AUTOMODE_CTRL#define PBI_AM_DIRRD            0x00010000#define PBI_AM_8BIT             0x00020000#define PBI_AM_IDEDMA           0x00040000#define PBI_AM_ENDIAN           0x00080000#define PBI_AM_IDE              0x00100000#define PBI_AM_MUXAD            0x00200000#define PBI_AM_BURST            0x00400000#define PBI_AM_CS0              0x00000000#define PBI_AM_CS1              0x01000000#define PBI_AM_CS2              0x02000000#define PBI_AM_CS3              0x03000000#endif