/* * linux/include/asm-arm/arch-atmel/hardware.h * for JASPER * Created 12/12/2001 Fabrice Gautier * Copyright 2001, Sigma Desings, Inc */#ifndef __ASM_ARCH_HARDWARE_H#define __ASM_ARCH_HARDWARE_H#define IO_ADDRESS(x) (x)// PLL input clock, typically 27 Mhz#define JASPER_EXT_CLOCK 27000000/* 0=TC0, 1=TC1, 2=TC2 *///------------------------------------------------------// SYSTEM CONTROLLER 0x0050_0000//------------------------------------------------------#define	    JASPER_SYSCTRL_BASE		0x00500000#define	    SYSCTRL_CHIP_ID		0x00000000#define	    SYSCTRL_REVISION_ID		0x00000008#define	    SYSCTRL_CPUCFG		0x0000000C#define	    SYSCTRL_TESTSTAT		0x00000010#define	    SYSCTRL_ERRSTAT		0x00000014#define	    SYSCTRL_BADADDR		0x00000018#define	    SYSCTRL_RSTCTL		0x00000020#define	    SYSCTRL_CPUTIMESLOT		0x00000024//------------------------------------------------------// TIMER 0 AND 1 0x0050_0100//-------------------------TIMER_-----------------------#define	    JASPER_TIMER_BASE		0x00500100#define     TIMER_TMRSTAT		0x00000000#define     TIMER_TMR0LOAD		0x00000010#define     TIMER_TMR0VAL		0x00000014#define     TIMER_TMR0CTL		0x00000018#define     TIMER_TMR1LOAD		0x00000020#define     TIMER_TMR1VAL		0x00000024#define     TIMER_TMR1CTL		0x00000028//------------------------------------------------------// INT CONTROLLER 0x0050_0200//------------------------------------------------------#define     JASPER_INT_CONTROLLER_BASE	0x00500200#define     INT_IRQSTAT			0x00000000#define     INT_FIQSTAT			0x00000004#define     INT_INTTYPE			0x00000010#define     INT_INTPOLL			0x00000020#define     INT_INTEN			0x00000024//------------------------------------------------------// MAC Registers 0x00500300//------------------------------------------------------#define     JASPER_MAC_BASE		0x00500300#define     MAC_REFTIMER		0x00000000#define     MAC_FLASH_CFG		0x00000014#define     MAC_FLASH_ST		0x0000001c#define     MAC_SDRAMCTL		0x00000020#define     MAC_SDRAMCFG		0x00000024#define     MAC_SDRAMDATA		0x00000028#define     MAC_SDRAMST			0x0000002c#define     MAC_ARBITERCTRL		0x00000090#define     MAC_ARBITERSTATE		0x00000094#define     MAC_WATCHDOG_CTRL		0x000000A0#define     MAC_WATCHDOG_TMO0		0x000000A4#define     MAC_WATCHDOG_TMO1		0x000000A8#define     MAC_WATCHDOG_INT		0x000000Ac#define     MAC_TIMESLOTCNT		0x000000B0//------------------------------------------------------// UART REGISTERs//	UART0 0050_0500//	UART1 0050_1300//------------------------------------------------------#define		JASPER_UART0_BASE	0x00500500#define		JASPER_UART1_BASE	0x00501300#define		UART_NR			2#define		UART_RBR		0x00#define		UART_TBR		0x04#define		UART_IER		0x08#define		UART_IIR		0x0C#define		UART_FCR		0x10#define		UART_LCR		0x14#define		UART_MCR		0x18#define		UART_LSR		0x1C#define		UART_MSR		0x20#define		UART_SCRATCH		0x24#define		UART_CLKDIV		0x28#define		UART_CLKSEL		0x2C//------------------------------------------------------// PIO0 block  0x0050_0600// PIO1 block  0x0050_0A00//------------------------------------------------------#define     JASPER_PIO0_BASE		0x00500600#define     JASPER_PIO1_BASE		0x00500A00#define     PIO_INT_STATUS		0x00000000#define     PIO_DATA			0x00000004#define     PIO_DIR			0x00000008#define     PIO_POL			0x0000000C#define     PIO_INT_ENABLE		0x00000010//------------------------------------------------------//    I2C MASTER REGISTERs	0X0050_0800//------------------------------------------------------#define		JASPER_I2C_MASTER_BASE		0x00500800#define		I2C_MASTER_CONFIG		0x00#define		I2C_MASTER_CLK_DIV		0x04#define		I2C_MASTER_DEV_ADDR		0x08#define		I2C_MASTER_ADR			0x0C#define		I2C_MASTER_DATAOUT		0x10#define		I2C_MASTER_DATAIN		0x14#define		I2C_MASTER_STATUS		0x18#define		I2C_MASTER_STARTXFER		0x1C#define		I2C_MASTER_BYTE_COUNT		0x20#define		I2C_MASTER_INTEN		0x24#define		I2C_MASTER_INT			0x28//------------------------------------------------------// I2C SLAVE REGISTERs	0X0050_0900//------------------------------------------------------#define		JASPER_I2C_SLAVE_BASE			0x00500900#define		I2C_SLAVE_ADDR				0x00#define		I2C_SLAVE_DATAOUT			0x04#define		I2C_SLAVE_DATAIN			0x08#define		I2C_SLAVE_STATUS			0x0C#define		I2C_SLAVE_INTEN				0x10#define		I2C_SLAVE_INT				0x14#define		I2C_SLAVE_BUS_HOLD			0x18//------------------------------------------------------// IDE_REGISTERs 0x0050_0B00//------------------------------------------------------#define		JASPER_IDE_BASE				0x00500B00#define		JASPER_IDE_DMA_BASE			0x00500E00			// **** DMA CHANNEL REG ****#define		IDE_BMIC				0x00	// ( 8 BIT) BMIC IDE COMMAND REG#define		IDE_BMIS				0x04	// ( 8 BIT) BMIC IDE STATUS REG#define		IDE_BMIDTP				0x08	// (32 BIT) BUSMASTER IDE DESCRIPTOR TABLE POINTER REG#define		IDE_TIM					0x40	// (16 BIT) IDE TIMING Reg#define		IDE_SIDETIM				0x48	// ( 8 BIT) SLAVE IDE TIMING Reg#define		IDE_SRC					0x4C	// (16 BIT) SLEW RATE CTRL Reg (45h-46h)#define		IDE_STATUS				0x50	// ( 8 BIT) IDESTATUS#define		IDE_UDMACTL				0x54	// ( 8 BIT) ULTRA DMA CONTORL Reg#define		IDE_UDMATIM				0x58	// (16 BIT) ULTRA DMA TIMING Reg (4A - 4B)#define		IDE_PRI_DEVICE_CONTROL			0xE6	// (16 BIT) Device 0:#define		IDE_PRI_DATA				0xF0	// (16 BIT) Device 0:#define		IDE_PRI_SECTOR_COUNT			0xF2	// (16 BIT) Device 0:#define		IDE_PRI_DEVICE_HEAD			0xF6	// (16 BIT) Device 0:#define		IDE_PRI_CMD				0xF7	// (16 BIT) Device 0://------------------------------------------------------// DVD-LOADER_REGISTERs 0x0050_0C00//------------------------------------------------------#define		JASPER_DVD_BASE				0x00500C00#define		DVD_AV_CTRL				0x00	// (16 BIT) AUDIO/VIDEO PART FROM HOST#define		DVD_AV_SEC_CNT				0x04	//#define		DVD_AV_BYTE_CNT				0x08	//#define		DVD_AV_INTMSK				0x0C	//#define		DVD_AV_INT				0x10	//#define		DVD_FIFO_LIM				0x14	//#define		DVD_TIMOUT_LIM				0x18	//#define		DVD_AV_X2C				0x1C	//#define		DVD_HOST_CTRL				0x20	//#define		DVD_HOST_SCLK				0x24	//#define		DVD_HOST_TXREG				0x28	//#define		DVD_HOST_RXREG				0x2C	////------------------------------------------------------// FIP REGISTERs 0x0050_0D00//------------------------------------------------------#define		JASPER_FIP_BASE				0x00500D00#define		FIP_COMMAND				0x00#define		FIP_DISPLAY_DATA			0x04#define		FIP_LED_DATA				0x08#define		FIP_KEY_DATA1				0x0C#define		FIP_KEY_DATA2				0x10#define		FIP_SWITCH_DATA				0x14#define		FIP_CLK_DIV				0x20#define		FIP_TRISTATE_MODE			0x24//------------------------------------------------------//    DVD-DMA REGISTERs  0x0050_0F00//------------------------------------------------------#define		JASPER_DVD_DMA_BASE			0x00500F00#define		DVD_DMACTL				0x00	//#define		DVD_DMAMSK				0x04	//#define		DVD_DMAINT				0x08	//#define		DVD_DMARAW				0x0C	//#define		DVD_RXADDR				0x10	//#define		DVD_RXBYTES				0x14	////------------------------------------------------------// RTC REGISTER	0x0050_1400//------------------------------------------------------#define		JASPER_RTC_BASE				0x00501400#define		RTC_CTRL				0x00000000#define		RTC_LOAD1				0x00000004#define		RTC_LOAD2				0x00000008#define		RTC_ALARM				0x0000000C#define		RTC_INTEN				0x00000010#define		RTC_INT0				0x00000014#define		RTC_COUNT1				0x00000018#define		RTC_COUNT2				0x0000001C//------------------------------------------------------// HOST/QUASAR SLAVE REGISTERS 0x0050_1500//------------------------------------------------------#define		JASPER_HOST_SLAVE_QUASAR_BASE	0x00501500#define		HOST_SLAVE_WR_QUASAR_BYTE	0x00000000#define		HOST_SLAVE_WR_QUASAR_1BYTE	0x00000000#define		HOST_SLAVE_WR_QUASAR_2BYTE	0x00000004#define		HOST_SLAVE_WR_QUASAR_3BYTE	0x00000008#define		HOST_SLAVE_WR_QUASAR_4BYTE	0x0000000C#define		HOST_SLAVE_RD_QUASAR_BYTE	0x00000000#define		HOST_SLAVE_RD_QUASAR_1BYTE	0x00000000#define		HOST_SLAVE_RD_QUASAR_2BYTE	0x00000004#define		HOST_SLAVE_RD_QUASAR_3BYTE	0x00000008#define		HOST_SLAVE_RD_QUASAR_4BYTE	0x0000000C//------------------------------------------------------// I2S REGISTERs 0x0050_1600//------------------------------------------------------#define		JASPER_I2S_BASE			0x00501600#define		I2S_CTRL			0x0#define		I2S_PROG_LEN			0x4#define		I2S_STATUS			0x8#define		I2S_FRAME_CNTR			0xC#define		I2S_RESET			0x2#define		I2S_ENABLE			0x1#define		I2S_MASTER_MODE			0x4#define		I2S_SCIN_DIV00			0x00#define		I2S_SCIN_DIV01			0x08#define		I2S_SCIN_DIV10			0x10#define		I2S_SCIN_DIV11			0x18