?? jasper.h
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#define FORCE_REMAP 0x1#define CPU_ACCESS_240_CLOCKS 0xF // 240 closck#define CPU_TIMEOUT_15_CLOCK 0xF // 15 clocks#define CPU_TIMESLOT_ENABLE 0x100 // Enable TIMESLOT mechanism//------------------------------------------------------// MAC COMMAND DEFINITIONS//------------------------------------------------------#define SDRAMCLK_EN 0x1#define SDRAMINI_SET 0x2//#define TIME_SLOT_4DW 0x0//#define TIME_SLOT_8DW 0x1//#define TIME_SLOT_16DW 0x2//#define TIME_SLOT_32DW 0x3#define TIME_SLOT_HIGH_ARBITRATION 0x10000#define TIME_SLOT_SLOW_ARBITRATION 0x000//------------------------------------------------------// TIMER COMMAND DEFINITIONS//------------------------------------------------------#define TIMER02IRQ 0xFFFFFFFE#define TIMER02FIQ 0x00000001#define TIMER12IRQ 0xFFFFFFFD#define TIMER12FIQ 0x00000002#define TIMER0_START 0x00000010#define TIMER1_START 0x00000020#define TIMER0_INT_CLR 0x00000001#define TIMER1_INT_CLR 0x00000002#define TIMER_FREE_RUN_MODE 0x00000000#define TIMER_PERIODIC_MODE 0x00000010#define TIMER_RUN_OUT_MODE 0x00000020#define TIMER_COUNT_ENABLE 0x00000080#define TIMER_NO_PRESCALE 0x0#define TIMER_PRESCALE_4 0x1#define TIMER_PRESCALE_8 0x2#define TIMER_PRESCALE_16 0x3#define TIMER_PRESCALE_32 0x4#define TIMER_PRESCALE_64 0x5#define TIMER_PRESCALE_128 0x6#define TIMER_PRESCALE_256 0x7#define TIMER_PRESCALE_512 0x8#define TIMER_PRESCALE_1024 0x9#define TIMER_PRESCALE_2048 0xA#define TIMER_PRESCALE_4096 0xB#define TIMER_PRESCALE_8192 0xC#define TIMER_PRESCALE_16384 0xD#define TIMER_PRESCALE_32768 0xE#define TIMER_PRESCALE_65536 0xF//------------------------------------------------------// SPI COMMAND DEFINITIONS//------------------------------------------------------#define SPI_ENABLE 0x1#define SPI_RESET 0x2#define SPI_RESET_ERR_CNTR 0x4#define SPI_DISABLE_ERR_CHECK 0x8#define SPI_STATUS_MASK 0x000070#define SPI_PKT_DONE 0x1#define SPI_SIZE_ERR 0x2#define SPI_SYNC_ERR 0x4#define SPI_HW_ERR 0x8//------------------------------------------------------// SPI/I2S-DMA COMMAND DEFINITIONS//------------------------------------------------------#define SPI_I2S_DMA_RESET 0x2#define SPI_I2S_DMA_EN 0x1#define SPI_I2S_INT_BUF_FULL 0x1#define SPI_I2S_INT_BUF_14 0x2#define SPI_I2S_INT_BUF_12 0x4#define SPI_I2S_INT_BUF_34 0x8#define SPI_I2S_CIR_EN 0x8 /* Enable circular buffer */#define SPI_I2S_MUX_SPI_SELECT 0x10#define SPI_I2S_FLASH_INTER_FIFO 0x4//------------------------------------------------------// FIP COMMAND DEFINITIONS //------------------------------------------------------#define FIP_CMD_DISP_MODE_08DIGITS_20SEGMENTS 0x00#define FIP_CMD_DISP_MODE_09DIGITS_19SEGMENTS 0x08#define FIP_CMD_DISP_MODE_10DIGITS_18SEGMENTS 0x09#define FIP_CMD_DISP_MODE_11DIGITS_17SEGMENTS 0x0a#define FIP_CMD_DISP_MODE_12DIGITS_16SEGMENTS 0x0b#define FIP_CMD_DISP_MODE_13DIGITS_15SEGMENTS 0x0c#define FIP_CMD_DISP_MODE_14DIGITS_14SEGMENTS 0x0d#define FIP_CMD_DISP_MODE_15DIGITS_13SEGMENTS 0x0e#define FIP_CMD_DISP_MODE_16DIGITS_12SEGMENTS 0x0f#define FIP_CMD_DATA_SET_RW_MODE_WRITE_DISPLAY 0x40#define FIP_CMD_DATA_SET_RW_MODE_WRITE_LED_PORT 0x41#define FIP_CMD_DATA_SET_RW_MODE_READ_KEYS 0x42#define FIP_CMD_DATA_SET_RW_MODE_READ_SWITCHES 0x43#define FIP_CMD_DATA_SET_ADR_MODE_INCREMENT_ADR 0x40#define FIP_CMD_DATA_SET_ADR_MODE_FIXED_ADR 0x44#define FIP_CMD_DATA_SET_OP_MODE_NORMAL_OPERATION 0x40#define FIP_CMD_DATA_SET_OP_MODE_TEST_MODE 0x48#define FIP_CMD_ADR_SETTING 0xC0#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_1_16 0x80#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_2_16 0x81#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_4_16 0x82#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_10_16 0x83#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_11_16 0x84#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_12_16 0x85#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_13_16 0x86#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_14_16 0x87#define FIP_CMD_DISP_CTRL_TURN_DISPLAY_OFF_MASK 0x87#define FIP_CMD_DISP_CTRL_TURN_DISPLAY_ON 0x88//---------------------------------------------------------------------------------------------// I/O Macro definitions//---------------------------------------------------------------------------------------------#define PRINT_STATUS *( (volatile unsigned int * )SimStatusAddress)#define VERILOG_STOP *( (volatile unsigned int * )SIMULATION_CONTROL) = SIMULATION_CMD_STOP_WITH_ERROR//---------------------------------------------------------------------------------------------// QuickTurn Macro definitions//---------------------------------------------------------------------------------------------#define WRITE_LED_DISPLAY PIO_0_DATA_REG#define WRITE_HEX_DISPLAY PIO_1_DATA_REG//---------------------------------------------------------------------------------------------// PIO Macro definitions//---------------------------------------------------------------------------------------------#define PIO_0_INT_STATUS_REG ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_INT_STATUS) )#define PIO_0_DATA_REG ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_DATA) )#define PIO_0_DIR_REG ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_DIR) )#define PIO_0_POL_REG ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_POL) )#define PIO_0_INT_ENABLE_REG ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_INT_ENABLE) )#define PIO_1_INT_STATUS_REG ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_INT_STATUS) )#define PIO_1_DATA_REG ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_DATA) )#define PIO_1_DIR_REG ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_DIR) )#define PIO_1_POL_REG ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_POL) )#define PIO_1_INT_ENABLE_REG ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_INT_ENABLE) )//---------------------------------------------------------------------------------------------// SPI_I2S_DMA Macro definitions//---------------------------------------------------------------------------------------------#define SPI_I2S_DMA_REG_CTRL ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_CTRL_REG) )#define SPI_I2S_DMA_REG_BASE_ADD ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_BASE_ADD_REG) )#define SPI_I2S_DMA_REG_SIZE ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_SIZE_REG) )#define SPI_I2S_DMA_REG_WR_PTR ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_WR_PTR_REG) )#define SPI_I2S_DMA_REG_RD_PTR ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_RD_PTR_REG) )#define SPI_I2S_DMA_REG_TRSH ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_TRSH_REG) )#define SPI_I2S_DMA_REG_INT_EN ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_INT_EN_REG) )#define SPI_I2S_DMA_REG_INT ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_INT_REG) )#define SPI_I2S_DMA_REG_INT_POLL ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_INT_POLL_REG) )#define SPI_I2S_DMA_REG_INTER_FIFO ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_INTER_FIFO_REG) )#define SPI_I2S_DMA_REG_CNT ( (volatile unsigned int * ) (SPI_I2S_DMA_BASE + SPI_I2S_DMA_CNT_REG) )//---------------------------------------------------------------------------------------------// Memory Access Controller (MAC) Macro definitions//---------------------------------------------------------------------------------------------#define MAC_REFTIMER_REG ( (volatile unsigned int * ) (MAC_base + MAC_REFTIMER) )#define MAC_FLASHCFG_REG ( (volatile unsigned int * ) (MAC_base + MAC_FLASH_CFG) )#define MAC_SDRAMCTL_REG ( (volatile unsigned int * ) (MAC_base + MAC_SDRAMCTL) )#define MAC_SDRAMCFG_REG ( (volatile unsigned int * ) (MAC_base + MAC_SDRAMCFG) )#define MAC_SDRAMDATA_REG ( (volatile unsigned int * ) (MAC_base + MAC_SDRAMDATA) )//---------------------------------------------------------------------------------------------// Interrupt Controller Macro definitions//---------------------------------------------------------------------------------------------#define INT_IRQSTAT_REG ( (volatile unsigned int * ) (JASPER_INT_CONTROLLER_BASE + INT_IRQSTAT) )#define INT_FIQSTAT_REG ( (volatile unsigned int * ) (JASPER_INT_CONTROLLER_BASE + INT_FIQSTAT) )#define INT_TYPE_REG ( (volatile unsigned int * ) (JASPER_INT_CONTROLLER_BASE + INT_INTTYPE) )#define INT_POLL_REG ( (volatile unsigned int * ) (JASPER_INT_CONTROLLER_BASE + INT_INTPOLL) )#define INT_ENABLE_REG ( (volatile unsigned int * ) (JASPER_INT_CONTROLLER_BASE + INT_INTEN) )//---------------------------------------------------------------------------------------------// SPI Registers Macro definitions//---------------------------------------------------------------------------------------------#define SPI_CNTR_REG ( (volatile unsigned int * ) (JASPER_SPI_BASE + SPI_CNTR) )#define SPI_REC_COUNTER_REG ( (volatile unsigned int * ) (JASPER_SPI_BASE + SPI_REC_COUNTER) )#define SPI_INT_EN_REG ( (volatile unsigned int * ) (JASPER_SPI_BASE + SPI_INT_EN) )#define SPI_INT_STATUS_REG ( (volatile unsigned int * ) (JASPER_SPI_BASE + SPI_INT_STATUS) )#define SPI_ERROR_CNT_REG ( (volatile unsigned int * ) (JASPER_SPI_BASE + SPI_ERROR_CNT) )//---------------------------------------------------------------------------------------------// I2S Registers Macro definitions//---------------------------------------------------------------------------------------------#define I2S_CNTR_REG ( (volatile unsigned int * ) (JASPER_I2S_BASE + I2S_CTRL) )#define I2S_PROG_LEN_REG ( (volatile unsigned int * ) (JASPER_I2S_BASE + I2S_PROG_LEN) )#define I2S_STATUS_REG ( (volatile unsigned int * ) (JASPER_I2S_BASE + I2S_STATUS) )#define I2S_FRAME_CNTR_REG ( (volatile unsigned int * ) (JASPER_I2S_BASE + I2S_FRAME_CNTR) )//---------------------------------------------------------------------------------------------// RTC Registers Macro definitions//---------------------------------------------------------------------------------------------#define RTC_CTRL_REG ( (volatile unsigned int * ) (JASPER_RTC_BASE + RTC_CTRL) )#define RTC_LOAD1_REG ( (volatile unsigned int * ) (JASPER_RTC_BASE + RTC_LOAD1) )#define RTC_LOAD2_REG ( (volatile unsigned int * ) (JASPER_RTC_BASE + RTC_LOAD2) )#define RTC_ALARM_REG ( (volatile unsigned int * ) (JASPER_RTC_BASE + RTC_ALARM) )#define RTC_INTEN_REG ( (volatile unsigned int * ) (JASPER_RTC_BASE + RTC_INTEN) )#define RTC_INT_REG ( (volatile unsigned int * ) (JASPER_RTC_BASE + RTC_INT0) )#define RTC_COUNT1_REG ( (volatile unsigned int * ) (JASPER_RTC_BASE + RTC_COUNT1) )#define RTC_COUNT2_REG ( (volatile unsigned int * ) (JASPER_RTC_BASE + RTC_COUNT2) )//---------------------------------------------------------------------------------------------// Timer Registers Macro definitions//---------------------------------------------------------------------------------------------#define TIMER_TMRSTAT_REG ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMRSTAT) )#define TIMER0_LOAD_REG ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR0LOAD) )#define TIMER0_VAL_REG ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR0VAL) )#define TIMER0_CNTL_REG ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR0CTL) )#define TIMER1_LOAD_REG ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR1LOAD) )#define TIMER1_VAL_REG ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR1VAL) )#define TIMER1_CNTL_REG ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR1CTL) )//---------------------------------------------------------------------------------------------// Interrupt Registers Macro definitions//---------------------------------------------------------------------------------------------/* XXX - defined twice - see above INT_xxx_REG#define INTERRUPT_IRQSTAT_REG ( (volatile unsigned int * ) (INT_CONTROLLER_BASE + INT_IRQSTAT) )#define INTERRUPT_FIQSTAT_REG ( (volatile unsigned int * ) (INT_CONTROLLER_BASE + INT_FIQSTAT) )#define INTERRUPT_INTTYPE_REG ( (volatile unsigned int * ) (INT_CONTROLLER_BASE + INT_INTTYPE) )#define INTERRUPT_POLL_REG ( (volatile unsigned int * ) (INT_CONTROLLER_BASE + INT_INTPOLL) )#define INTERRUPT_ENABLE_REG ( (volatile unsigned int * ) (INT_CONTROLLER_BASE + INT_INTEN) )*///---------------------------------------------------------------------------------------------// System Registers Macro definitions//---------------------------------------------------------------------------------------------#define SYS_CHIPID_REG ( (volatile unsigned int * ) (JASPER_SYSCTRL_BASE + SYSCTRL_CHIPID) )#define SYS_CPU_CFG_REG ( (volatile unsigned int * ) (JASPER_SYSCTRL_BASE + SYSCTRL_CPUCFG) )#define SYS_TESTSTAT_REG ( (volatile unsigned int * ) (JASPER_SYSCTRL_BASE + SYSCTRL_TESTSTAT) )#define SYS_RESET_REG ( (volatile unsigned int * ) (JASPER_SYSCTRL_BASE + SYSCTRL_RSTCTL) )#define SYS_TIMESLOT_REG ( (volatile unsigned int * ) (JASPER_SYSCTRL_BASE + SYSCTRL_CPUTIMESLOT) )//---------------------------------------------------------------------------------------------// FIP Registers Macro definitions//---------------------------------------------------------------------------------------------#define FIP_COMMAND_REG ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_COMMAND) )#define FIP_DISPLAY_DATA_REG ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_DISPLAY_DATA) )#define FIP_LED_DATA_REG ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_LED_DATA) )#define FIP_KEY_DATA1_REG ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_KEY_DATA1) )#define FIP_KEY_DATA2_REG ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_KEY_DATA2) )#define FIP_SWITCH_DATA_REG ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_SWITCH_DATA) )#define FIP_CLK_DIV_REG ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_CLK_DIV) )#define FIP_TRISTATE_MODE_REG ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_TRISTATE_MODE) )#endif /* _ASM_ARCH_HARDWARE_H */?? 快捷鍵說明
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