/*
	FreeRTOS.org V4.1.1 - copyright (C) 2003-2006 Richard Barry.

	This file is part of the FreeRTOS.org distribution.

	FreeRTOS.org is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	FreeRTOS.org is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with FreeRTOS.org; if not, write to the Free Software
	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

	A special exception to the GPL can be applied should you wish to distribute
	a combined work that includes FreeRTOS.org, without being obliged to provide
	the source code for any proprietary components.  See the licensing section 
	of http://www.FreeRTOS.org for full details of how and when the exception
	can be applied.

	***************************************************************************
	See http://www.FreeRTOS.org for documentation, latest information, license 
	and contact details.  Please ensure to read the configuration and relevant 
	port sections of the online documentation.
	***************************************************************************
*/

/*
	Changes from V3.2.3
	
	+ Modified char* types to compile without warning when using GCC V4.0.1.
	+ Corrected the address to which the MAC address is written.  Thanks to
	  Bill Knight for this correction.

	Changes from V3.2.4

	+ Changed the default MAC address to something more realistic.

*/

/* Standard includes. */
#include <stdlib.h>
#include <string.h>

/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#include "tcp.h"
#include "serial.h"

/* Application includes. */
#include "i2c.h"
#include "html_pages.h"

/*-----------------------------------------------------------*/

/* Hardwired i2c address of the WIZNet device. */
#define tcpDEVICE_ADDRESS 				( ( unsigned portCHAR ) 0x00 )

/* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
device. */
#define tcp8K_RX						( ( unsigned portCHAR ) 0x03 )
#define tcp8K_TX						( ( unsigned portCHAR ) 0x03 )

/* Constants used to generate the WIZnet internal buffer addresses. */
#define tcpSINGLE_SOCKET_ADDR_MASK		( ( unsigned portLONG ) 0x1fff )
#define tcpSINGLE_SOCKET_ADDR_OFFSET	( ( unsigned portLONG ) 0x4000 )

/* Bit definitions of the commands that can be sent to the command register. */
#define tcpRESET_CMD					( ( unsigned portCHAR ) 0x80 )
#define tcpSYS_INIT_CMD					( ( unsigned portCHAR ) 0x01 )
#define tcpSOCK_STREAM					( ( unsigned portCHAR ) 0x01 )
#define tcpSOCK_INIT					( ( unsigned portCHAR ) 0x02 )
#define tcpLISTEN_CMD					( ( unsigned portCHAR ) 0x08 )
#define tcpRECEIVE_CMD					( ( unsigned portCHAR ) 0x40 )
#define tcpDISCONNECT_CMD				( ( unsigned portCHAR ) 0x10 )
#define tcpSEND_CMD						( ( unsigned portCHAR ) 0x20 )

/* Constants required to handle the interrupts. */
#define tcpCLEAR_EINT0					( 1 )
#define i2cCLEAR_ALL_INTERRUPTS			( ( unsigned portCHAR ) 0xff )
#define i2cCHANNEL_0_ISR_ENABLE			( ( unsigned portCHAR ) 0x01 )
#define i2cCHANNEL_0_ISR_DISABLE		( ( unsigned portCHAR ) 0x00 )
#define tcpWAKE_ON_EINT0				( 1 )
#define tcpENABLE_EINT0_FUNCTION		( ( unsigned portLONG ) 0x01 )
#define tcpEINT0_VIC_CHANNEL_BIT		( ( unsigned portLONG ) 0x4000 )
#define tcpEINT0_VIC_CHANNEL			( ( unsigned portLONG ) 14 )
#define tcpEINT0_VIC_ENABLE				( ( unsigned portLONG ) 0x0020 )

/* Various delays used in the driver. */
#define tcpRESET_DELAY					( ( portTickType ) 16 / portTICK_RATE_MS )
#define tcpINIT_DELAY					( ( portTickType ) 500 / portTICK_RATE_MS  )
#define tcpLONG_DELAY					( ( portTickType ) 500 / portTICK_RATE_MS  )
#define tcpSHORT_DELAY					( ( portTickType ) 5 / portTICK_RATE_MS )
#define tcpCONNECTION_WAIT_DELAY		( ( portTickType ) 100 / portTICK_RATE_MS )
#define tcpNO_DELAY						( ( portTickType ) 0 )

/* Length of the data to read for various register reads. */
#define tcpSTATUS_READ_LEN				( ( unsigned portLONG ) 1 )
#define tcpSHADOW_READ_LEN				( ( unsigned portLONG ) 1 )
	
/* Register addresses within the WIZnet device. */
#define tcpCOMMAND_REG					( ( unsigned portSHORT ) 0x0000 )
#define tcpGATEWAY_ADDR_REG				( ( unsigned portSHORT ) 0x0080 )
#define tcpSUBNET_MASK_REG				( ( unsigned portSHORT ) 0x0084 )
#define tcpSOURCE_HA_REG				( ( unsigned portSHORT ) 0x0088 )
#define tpcSOURCE_IP_REG				( ( unsigned portSHORT ) 0x008E )
#define tpcSOCKET_OPT_REG				( ( unsigned portSHORT ) 0x00A1 )
#define tcpSOURCE_PORT_REG				( ( unsigned portSHORT ) 0x00AE )
#define tcpTX_WRITE_POINTER_REG			( ( unsigned portSHORT ) 0x0040 )
#define tcpTX_READ_POINTER_REG			( ( unsigned portSHORT ) 0x0044 )
#define tcpTX_ACK_POINTER_REG			( ( unsigned portSHORT ) 0x0018 )
#define tcpTX_MEM_SIZE_REG				( ( unsigned portSHORT ) 0x0096 )
#define tcpRX_MEM_SIZE_REG				( ( unsigned portSHORT ) 0x0095 )
#define tcpINTERRUPT_STATUS_REG			( ( unsigned portSHORT ) 0x0004 )
#define tcpTX_WRITE_SHADOW_REG			( ( unsigned portSHORT ) 0x01F0 )
#define tcpTX_ACK_SHADOW_REG			( ( unsigned portSHORT ) 0x01E2 )
#define tcpISR_MASK_REG					( ( unsigned portSHORT ) 0x0009 )
#define tcpINTERRUPT_REG				( ( unsigned portSHORT ) 0x0008 )
#define tcpSOCKET_STATE_REG				( ( unsigned portSHORT ) 0x00a0 )

/* Constants required for hardware setup. */
#define tcpRESET_ACTIVE_LOW 			( ( unsigned portLONG ) 0x20 )
#define tcpRESET_ACTIVE_HIGH 			( ( unsigned portLONG ) 0x10 )

/* Constants defining the source of the WIZnet ISR. */
#define tcpISR_SYS_INIT					( ( unsigned portCHAR ) 0x01 )
#define tcpISR_SOCKET_INIT				( ( unsigned portCHAR ) 0x02 )
#define tcpISR_ESTABLISHED				( ( unsigned portCHAR ) 0x04 )
#define tcpISR_CLOSED					( ( unsigned portCHAR ) 0x08 )
#define tcpISR_TIMEOUT					( ( unsigned portCHAR ) 0x10 )
#define tcpISR_TX_COMPLETE				( ( unsigned portCHAR ) 0x20 )
#define tcpISR_RX_COMPLETE				( ( unsigned portCHAR ) 0x40 )

/* Constants defining the socket status bits. */
#define tcpSTATUS_ESTABLISHED			( ( unsigned portCHAR ) 0x06 )
#define tcpSTATUS_LISTEN				( ( unsigned portCHAR ) 0x02 )

/* Misc constants. */
#define tcpNO_STATUS_BITS				( ( unsigned portCHAR ) 0x00 )
#define i2cNO_ADDR_REQUIRED				( ( unsigned portSHORT ) 0x0000 )
#define i2cNO_DATA_REQUIRED				( 0x0000 )
#define tcpISR_QUEUE_LENGTH				( ( unsigned portBASE_TYPE ) 10 )
#define tcpISR_QUEUE_ITEM_SIZE			( ( unsigned portBASE_TYPE ) 0 )
#define tcpBUFFER_LEN					( 4 * 1024 )
#define tcpMAX_REGISTER_LEN				( 4 )
#define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER	( 6 )
#define tcpMAX_NON_LISTEN_STAUS_READS	( 5 )

/* Message definitions.  The IP address, MAC address, gateway address, etc.
is set here! */
const unsigned portCHAR const ucDataGAR[]				= { 172, 25, 218, 3 };	/* Gateway address. */
const unsigned portCHAR const ucDataMSR[]				= { 255, 255, 255, 0 };	/* Subnet mask.		*/
const unsigned portCHAR const ucDataSIPR[]				= { 172, 25, 218, 201 };/* IP address.		*/
const unsigned portCHAR const ucDataSHAR[]				= { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */

/* Other fixed messages. */
const unsigned portCHAR const ucDataReset[]				= { tcpRESET_CMD }; 
const unsigned portCHAR const ucDataInit[]				= { tcpSYS_INIT_CMD }; 
const unsigned portCHAR const ucDataProtocol[]			= { tcpSOCK_STREAM };
const unsigned portCHAR const ucDataPort[]				= { 0xBA, 0xCC };
const unsigned portCHAR const ucDataSockInit[]			= { tcpSOCK_INIT };
const unsigned portCHAR const ucDataTxWritePointer[]	= { 0x11, 0x22, 0x00, 0x00 };
const unsigned portCHAR const ucDataTxAckPointer[]		= { 0x11, 0x22, 0x00, 0x00 };
const unsigned portCHAR const ucDataTxReadPointer[]		= { 0x11, 0x22, 0x00, 0x00 };
const unsigned portCHAR const ucDataListen[]			= { tcpLISTEN_CMD };
const unsigned portCHAR const ucDataReceiveCmd[]		= { tcpRECEIVE_CMD };
const unsigned portCHAR const ucDataSetTxBufSize[]		= { tcp8K_TX };
const unsigned portCHAR const ucDataSetRxBufSize[] 		= { tcp8K_RX };
const unsigned portCHAR const ucDataSend[]				= { tcpSEND_CMD };
const unsigned portCHAR const ucDataDisconnect[]		= { tcpDISCONNECT_CMD };
const unsigned portCHAR const ucDataEnableISR[]			= { i2cCHANNEL_0_ISR_ENABLE };
const unsigned portCHAR const ucDataDisableISR[]		= { i2cCHANNEL_0_ISR_DISABLE };
const unsigned portCHAR const ucDataClearInterrupt[]	= { i2cCLEAR_ALL_INTERRUPTS };

static xSemaphoreHandle xMessageComplete = NULL;
xQueueHandle xTCPISRQueue = NULL;

/* Dynamically generate and send an html page. */
static void prvSendSamplePage( void );

/* Read a register from the WIZnet device via the i2c interface. */
static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength );

/* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
static void prvFlushBuffer( unsigned portLONG ulTxAddress );

/* Write a string to the WIZnet Tx buffer. */
static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress );

/* Convert a number to a string. */
void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore );

/*-----------------------------------------------------------*/

void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore )
{
unsigned portLONG lNibble;
portLONG lIndex;

	/* Simple routine to convert an unsigned long value into a string in hex 
	format. */

	/* For each nibble in the number we are converting. */
	for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
	{
		/* Take the top four bits of the number. */
		lNibble = ( ulVal >> 28 );

		/* We are converting it to a hex string, so is the number in the range
		0-10 or A-F? */
		if( lNibble < 10 )
		{
			pcBuffer[ lIndex ] = '0' + lNibble;
		}
		else
		{
			lNibble -= 10;
			pcBuffer[ lIndex ] = 'A' + lNibble;
		}

		/* Shift off the top nibble so we use the next nibble next time around. */
		ulVal <<= 4;
	}	

	/* Mark the end of the string with a null terminator. */
	pcBuffer[ lIndex ] = 0x00;
}
/*-----------------------------------------------------------*/

static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength )
{
unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ];

	/* Read a register value from the WIZnet device. */

	/* First write out the address of the register we want to read. */
	i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
	
	/* Then read back from that address. */
	i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );

	/* I2C messages are queued so use the semaphore to wait for the read to 
	complete - otherwise we will leave this function before the I2C 
	transactions have completed. */
	xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
}
/*-----------------------------------------------------------*/

void vTCPHardReset( void )
{
	/* Physical reset of the WIZnet device by using the GPIO lines to hold the 
	WIZnet reset lines active for a few milliseconds. */

	/* Make sure the interrupt from the WIZnet is disabled. */
	VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;

	/* If xMessageComplete is NULL then this is the first time that this 
	function has been called and the queue and semaphore used in this file
	have not yet been created. */
	if( xMessageComplete == NULL )
	{
		/* Create and obtain the semaphore used when we want to wait for an i2c
		message to be completed. */
		vSemaphoreCreateBinary( xMessageComplete );
		xSemaphoreTake( xMessageComplete, tcpNO_DELAY );

		/* Create the queue used to communicate between the WIZnet and TCP tasks. */
		xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
	}

	/* Use the GPIO to reset the network hardware. */
	GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
	GPIO_IOSET = tcpRESET_ACTIVE_HIGH;

	/* Delay with the network hardware in reset for a short while. */
	vTaskDelay( tcpRESET_DELAY );

	GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
	GPIO_IOSET = tcpRESET_ACTIVE_LOW;

	vTaskDelay( tcpINIT_DELAY );

	/* Setup the EINT0 to interrupt on required events from the WIZnet device.
	First enable the EINT0 function of the pin. */
	PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
	
	/* We want the TCP comms to wake us from power save. */
	SCB_EXTWAKE = tcpWAKE_ON_EINT0;

	/* Install the ISR into the VIC - but don't enable it yet! */
	portENTER_CRITICAL();
	{
		extern void ( vEINT0_ISR )( void );

		VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
		VICVectAddr3 = ( portLONG ) vEINT0_ISR;

		VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
	}
	portEXIT_CRITICAL();

	/* Enable interrupts in the WIZnet itself. */
	i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );

	vTaskDelay( tcpLONG_DELAY );
}
/*-----------------------------------------------------------*/

portLONG lTCPSoftReset( void )
{
unsigned portCHAR ucStatus;
extern volatile portLONG lTransactionCompleted;

	/* Send a message to the WIZnet device to tell it set all it's registers
	back to their default states.  Then setup the WIZnet device as required. */

	/* Reset the internal WIZnet registers. */
	i2cMessage( ucDataReset,	sizeof( ucDataReset ),	tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );

	/* Now we can configure the protocol.   Here the MAC address, gateway 
	address, subnet mask and IP address are configured. */
	i2cMessage( ucDataSHAR,		sizeof( ucDataSHAR ),	tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
	i2cMessage( ucDataGAR,		sizeof( ucDataGAR ),	tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
	i2cMessage( ucDataMSR,		sizeof( ucDataMSR ),	tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG,	i2cWRITE, NULL, portMAX_DELAY );
	i2cMessage( ucDataSIPR,		sizeof( ucDataSIPR ),	tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG,	i2cWRITE, NULL, portMAX_DELAY );
	
	/* Next the memory buffers are configured to give all the WIZnet internal
	memory over to a single socket.  This gives the socket the maximum internal
	Tx and Rx buffer space. */
	i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
	i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );

	/* Send the sys init command so the above parameters take effect. */
	i2cMessage( ucDataInit,		sizeof( ucDataInit ),	tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );

	/* Seems to like a little wait here. */
	vTaskDelay( tcpINIT_DELAY );

	/* Read back the status to ensure the system initialised ok. */
	prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );

	/* We should find that the sys init was successful. */
	if( ucStatus != tcpISR_SYS_INIT )
	{
		return ( portLONG ) pdFAIL;
	}

	/* No i2c errors yet. */
	portENTER_CRITICAL();
		lTransactionCompleted = pdTRUE;
	portEXIT_CRITICAL();

	return ( portLONG ) pdPASS;
}
/*-----------------------------------------------------------*/

portLONG lTCPCreateSocket( void )
{
unsigned portCHAR ucStatus;

	/* Create and configure a socket. */

	/* Setup and init the socket.  Here the port number is set and the socket
	is initialised. */