?? 91x_map.h
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vu32 TXTCR; /* Tx DMA Current Transfer Count Register */
vu32 TXTOR; /* Tx DMA FIFO Time Out Register */
vu32 TXSR; /* Tx DMA FIFO Status Register */
} ENET_DMA_TypeDef;
/*------------------------------------- GPIO ---------------------------------*/
typedef struct
{
vu8 DR[1021]; /* Data Register */
vu32 DDR; /* Data Direction Register */
} GPIO_TypeDef;
/*-------------------------------- I2C interface -----------------------------*/
typedef struct
{
vu8 CR; /* Control Register */
vu8 EMPTY1[3];
vu8 SR1; /* Status Register 1 */
vu8 EMPTY2[3];
vu8 SR2; /* Status Register 2 */
vu8 EMPTY3[3];
vu8 CCR; /* Clock Control Register */
vu8 EMPTY4[3];
vu8 OAR1; /* Own Address Register 1 */
vu8 EMPTY5[3];
vu8 OAR2; /* Own Address Register 2 */
vu8 EMPTY6[3];
vu8 DR; /* Data Register */
vu8 EMPTY7[3];
vu8 ECCR; /* Extended Clock Control Register */
vu8 EMPTY8[3];
} I2C_TypeDef;
/*------------------------------------- VIC ----------------------------------*/
typedef struct
{
vu32 ISR; /* IRQ Status Register */
vu32 FSR; /* FIQ Status Register */
vu32 RINTSR; /* Raw Interrupt Status Register */
vu32 INTSR; /* Interrupt Select Register */
vu32 INTER; /* Interrupt Enable Register */
vu32 INTECR; /* Interrupt Enable Clear Register */
vu32 SWINTR; /* Software Interrupt Register */
vu32 SWINTCR; /* Software Interrupt clear Register */
vu32 PER; /* Protection Enable Register */
vu32 EMPTY1[3];
vu32 VAR; /* Vector Address Register */
vu32 DVAR; /* Default Vector Address Register */
vu32 EMPTY2[50];
vu32 VAiR[16]; /* Vector Address 0-15 Register */
vu32 EMPTY3[48];
vu32 VCiR[16]; /* Vector Control 0-15 Register */
} VIC_TypeDef;
/*-------------------------------- Motor Control -----------------------------*/
typedef struct
{
vu16 TCPT; /* Tacho Capture Register */
vu16 EMPTY1;
vu16 TCMP; /* Tacho Compare Register */
vu16 EMPTY2;
vu16 IPR; /* Input Pending Register */
vu16 EMPTY3;
vu16 TPRS; /* Tacho Prescaler Register */
vu16 EMPTY4;
vu16 CPRS; /* PWM Counter Prescaler Register */
vu16 EMPTY5;
vu16 REP; /* Repetition Counter Register */
vu16 EMPTY6;
vu16 CMPW; /* Compare Phase W Preload Register */
vu16 EMPTY7;
vu16 CMPV; /* Compare Phase V Preload Register */
vu16 EMPTY8;
vu16 CMPU; /* Compare Phase U Preload Register */
vu16 EMPTY9;
vu16 CMP0; /* Compare 0 Preload Register */
vu16 EMPTY10;
vu16 PCR0; /* Peripheral Control Register 0 */
vu16 EMPTY11;
vu16 PCR1; /* Peripheral Control Register 1 */
vu16 EMPTY12;
vu16 PCR2; /* Peripheral Control Register 2 */
vu16 EMPTY13;
vu16 PSR; /* Polarity Selection Register */
vu16 EMPTY14;
vu16 OPR; /* Output Peripheral Register */
vu16 EMPTY15;
vu16 IMR; /* Interrupt Mask Register */
vu16 EMPTY16;
vu16 DTG; /* Dead Time Generator Register */
vu16 EMPTY17;
vu16 ESC; /* Emergency Stop Clear Register */
vu16 EMPTY18;
}MC_TypeDef;
/*------------------------------------- RTC ----------------------------------*/
typedef struct
{
vu32 TR; /* Time Register */
vu32 DTR; /* Date Register */
vu32 ATR; /* Alarm time Register */
vu32 CR; /* Control Register */
vu32 SR; /* Status Register */
vu32 MILR; /* Millisec Register */
}RTC_TypeDef;
/*------------------------------------- SSP ----------------------------------*/
typedef struct
{
vu16 CR0; /* Control Register 1 */
vu16 EMPTY1;
vu16 CR1; /* Control Register 2 */
vu16 EMPTY2;
vu16 DR; /* Data Register */
vu16 EMPTY3;
vu16 SR; /* Status Register */
vu16 EMPTY4;
vu16 PR; /* Clock Prescale Register */
vu16 EMPTY5;
vu16 IMSCR; /* Interrupt Mask Set or Clear Register */
vu16 EMPTY6;
vu16 RISR; /* Raw Interrupt Status Register */
vu16 EMPTY7;
vu16 MISR; /* Masked Interrupt Status Register */
vu16 EMPTY8;
vu16 ICR; /* Interrupt Clear Register */
vu16 EMPTY9;
vu16 DMACR; /* DMA Control Register */
vu16 EMPTY10;
}SSP_TypeDef;
/*------------------------------------ UART ----------------------------------*/
typedef struct
{
vu16 DR; /* Data Register */
vu16 EMPTY1;
vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */
vu16 EMPTY2[9];
vu16 FR; /* Flag Register */
vu16 EMPTY3[3];
vu16 ILPR; /* IrDA Low-Power counter Register */
vu16 EMPTY4;
vu16 IBRD; /* Integer Baud Rate Divisor Register */
vu16 EMPTY5;
vu16 FBRD; /* Fractional Baud Rate Divisor Register */
vu16 EMPTY6;
vu16 LCR; /* Line Control Register, High byte */
vu16 EMPTY7;
vu16 CR; /* Control Register */
vu16 EMPTY8;
vu16 IFLS; /* Interrupt FIFO Level Select Register */
vu16 EMPTY9;
vu16 IMSC; /* Interrupt Mask Set/Clear Register */
vu16 EMPTY10;
vu16 RIS; /* Raw Interrupt Status Register */
vu16 EMPTY11;
vu16 MIS; /* Masked Interrupt Status Register */
vu16 EMPTY12;
vu16 ICR; /* Interrupt Clear Register */
vu16 EMPTY13;
vu16 DMACR; /* DMA Control Register */
vu16 EMPTY14;
}UART_TypeDef;
/*------------------------------- Wake-up System -----------------------------*/
typedef struct
{
vu32 CTRL; /* Control Register */
vu32 MR; /* Mask Register */
vu32 TR; /* Trigger Register */
vu32 PR; /* Pending Register */
vu32 INTR; /* Software Interrupt Register */
} WIU_TypeDef;
/*------------------------------- WatchDog Timer -----------------------------*/
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 PR; /* Presclar Register */
vu16 EMPTY2;
vu16 VR; /* Pre-load Value Register */
vu16 EMPTY3;
vu16 CNT; /* Counter Register */
vu16 EMPTY4;
vu16 SR; /* Status Register */
vu16 EMPTY5;
vu16 MR; /* Mask Register */
vu16 EMPTY6;
vu16 KR; /* Key Register */
vu16 EMPTY7;
} WDG_TypeDef;
/*******************************************************************************
* Memory Mapping of STR91x *
*******************************************************************************/
#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */
#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */
#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */
#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */
#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */
#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */
#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */
#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */
#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */
#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */
#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */
#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */
#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */
#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */
#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */
#define AHB_FMI_B (0x44000000) /* FMI buffered Space */
/*******************************************************************************
* Addresses related to the VICs' peripherals *
*******************************************************************************/
#define VIC0_BASE (AHB_VIC0_U)
#define VIC1_BASE (AHB_VIC1_U)
/*******************************************************************************
* Addresses related to the EMI banks *
*******************************************************************************/
#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */
#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */
#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */
#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */
/*******************************************************************************
* Addresses related to the DMA peripheral *
*******************************************************************************/
#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */
#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */
#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */
#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */
#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */
#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */
#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */
#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */
/*******************************************************************************
* Addresses related to the APB0 sub-system *
*******************************************************************************/
#define APB_WIU_OFST (0x00001000) /* Offset of WIU */
#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */
#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */
#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */
#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */
#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */
#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */
#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */
#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */
#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */
#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */
#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */
#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */
#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */
#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */
/*******************************************************************************
* Addresses related to the APB1 sub-system *
*******************************************************************************/
#define APB_RTC_OFST (0x00001000) /* Offset of RTC */
#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */
#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */
#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */
#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */
#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */
#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */
#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */
#define APB_CAN_OFST (0x00009000) /* Offset of CAN */
#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */
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