/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name          : 91x_enet.h
* Author             : MCD Application Team
* Date First Issued  : May 2006
* Description        : ENET driver defines & function prototypes
********************************************************************************
* History:
* May 2006: v1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/

#ifndef _ENET_H_
#define _ENET_H_

#include <91x_lib.h>

#define ENET_BUFFER_SIZE 1520
/*Structures typedef----------------------------------------------------------*/

/*Struct containing the DMA Descriptor data */
typedef struct  {
  volatile u32 dmaStatCntl;           /* DMA Status and Control Register          */
  volatile u32 dmaAddr;               /* DMA Start Address Register               */
  volatile u32 dmaNext;               /* DMA Next Descriptor Register             */
  volatile u32 dmaPackStatus;         /* DMA Packet Status and Control Register   */
} ENET_DMADSCRBase;


/* ENET_MACConfig Struct*/
typedef struct {
  FunctionalState ReceiveALL;                 /* Receive All frames: no address rule filtering */
  u32             MIIPrescaler;               /* MII Clock Prescaler value */
  FunctionalState LoopbackMode;               /* MAC Loopback mode */
  u32             AddressFilteringMode;       /* Address Filtering Mode */
  u32             VLANFilteringMode;          /* VLAN Filtering Mode */
  FunctionalState PassWrongFrame;             /* Pass wrong frame (CRC, overlength, runt..)*/
  FunctionalState LateCollision;              /* Retransmit frame when late collision*/
  FunctionalState BroadcastFrameReception;    /* Accept broardcast frame */
  FunctionalState PacketRetry;                /* Retransmit frame in case of collision */
  FunctionalState RxFrameFiltering;           /* Filter early runt frame and address filter fail frames*/
  FunctionalState AutomaticPadRemoval;        /* Automatic Padding removal */
  FunctionalState DeferralCheck;              /* Excessive Defferal check */
} ENET_MACConfig;

/* ENET_TxStatus Struct*/
typedef struct {
  FlagStatus PacketRetry;
  u8         ByteCount;
  u8         collisionCount;
  FlagStatus LateCollisionObserved;
  FlagStatus Deffered;
  FlagStatus UnderRun;
  FlagStatus ExcessiveCollision;
  FlagStatus LateCollision;
  FlagStatus ExcessiveDefferal;
  FlagStatus LossOfCarrier;
  FlagStatus NoCarrier;
  FlagStatus FrameAborted;
} ENET_TxStatus;

/* ENET_RxStatus Struct*/
typedef struct {
  FlagStatus FrameAborted;
  FlagStatus PacketFilter;
  FlagStatus FilteringFail;
  FlagStatus BroadCastFrame;
  FlagStatus MulticastFrame;
  FlagStatus UnsupportedControFrame;
  FlagStatus ControlFrame;
  FlagStatus LengthError;
  FlagStatus Vlan2Tag;
  FlagStatus Vlan1Tag;
  FlagStatus CRCError;
  FlagStatus ExtraBit;
  FlagStatus MIIError;
  FlagStatus FrameType;
  FlagStatus LateCollision;
  FlagStatus OverLength;
  FlagStatus RuntFrame;
  FlagStatus WatchDogTimout;
  FlagStatus FalseCarrierIndication;
  u16        FrameLength;
} ENET_RxStatus;

/*Constants-------------------------------------------------------------------*/


/* AddressFilteringMode */
#define MAC_Perfect_Multicast_Perfect 0x0
#define MAC_Perfect_Muticast_Hash     0x1<<17
#define MAC_Hash_Multicast_Hash       0x3<<17
#define Inverse                       0x4<<17
#define Promiscuous                   0x5<<17
#define MAC_Hash_Muticast_All         0x6<<17

/* VLANFilteringMode */
#define VLANFilter_VLTAG_VLID        1
#define VLANfilter_VLTAG             0

/* MIIPrescaler */
#define MIIPrescaler_1  0       /* Prescaler for MDC clock when HCLK < 50 MHz */
#define MIIPrescaler_2  1       /* Precaler for MDC when HCLK > = 50 MHz */


/* MAC Address*/
#define MAC_ADDR0 0x0D
#define MAC_ADDR1 0x0A
#define MAC_ADDR2 0x08
#define MAC_ADDR3 0x04
#define MAC_ADDR4 0x02
#define MAC_ADDR5 0x01

/* Multicast Address */
#define MCAST_ADDR0   0xFF
#define MCAST_ADDR1   0x00
#define MCAST_ADDR2   0xFF
#define MCAST_ADDR3   0x00
#define MCAST_ADDR4   0xFF
#define MCAST_ADDR5   0x00



#define ENET_MAX_PACKET_SIZE 1520
#define ENET_NEXT_ENABLE	0x4000

/*ENET_OperatingMode*/
/* Set the full/half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_100M       0x2100
#define PHY_HALFDUPLEX_100M       0x2000
/* Set the full/half-duplex mode at 10 Mb/s */
#define PHY_FULLDUPLEX_10M        0x0100
#define PHY_HALFDUPLEX_10M        0x0000


/*----------------------------functions----------------------------------------*/

void ENET_MACControlConfig(ENET_MACConfig *MAC_Config);
void ENET_GetRxStatus(ENET_RxStatus * RxStatus);
void ENET_GetTxStatus(ENET_TxStatus * TxStatus);
long ENET_SetOperatingMode(void);
void ENET_InitClocksGPIO(void);
void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32  phyVal);
u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg );
void ENET_RxDscrInit(void);
void ENET_TxDscrInit(void);
void ENET_Init(void);
void ENET_Start(void);
u32 ENET_RxPacketGetSize(void);
void ENET_TxPkt(void *ppkt, u16 size);
u32 ENET_HandleRxPkt(void *ppkt);


/*Driver internal constants---------------------------------------------------*/

/* MII Address */
/* Description of bit field values of the MII Address Register */
#define MAC_MIIA_PADDR         0x0000F800
#define MAC_MII_ADDR_PHY_ADDR  MAC_MIIA_PADDR /* Phy Address (default: 0): select one of 32 dev */
#define MAC_MII_ADDR_MII_REG   0x000007C0          /* MII Register (default: 0) */
#define MAC_MII_ADDR_MII_WRITE 0x00000002          /* MII Write */
#define MAC_MIIA_PHY_DEV_ADDR  (0x00005000 & MAC_MIIA_PADDR)  /*To be changed if PHY device address changes */
#define MAC_MII_ADDR_MII_BUSY  0x00000001 /* MII Busy */


/* MII DATA register */
#define MAC_MII_DATA_REG  0x0000FFFF /* MII Data */

/* MII Read / write timeouts*/
#define MII_READ_TO   0x0004FFFF
#define MII_WRITE_TO  0x0004FFFF

/* Description of common PHY registers */
#define MAC_MII_REG_XCR    0x00000000 /* Tranceiver control register */