/* romInit.s - Samsung SBC ARM7 ROM initialization module *//* Copyright 1984-2001 Wind River Systems, Inc. *//*modification history--------------------01f,18jan02,m_h  CLKCON initialization (74497), _sdata for vxWorks.res*01e,30nov01,m_h  additional label with "_" on entry point functions01d,15oct01,jb  Removing pre-pended underscores for new compilers (Diab/Gnu                 elf)01c,26apr01,m_h  fix thumb mode01b,26apr01,m_h  convert tabs to spaces for readability01a,12apr01,m_h  created from snds100 template.*//*DESCRIPTIONThis module contains the entry code for VxWorks images that startrunning from ROM, such as 'bootrom' and 'vxWorks_rom'.  The entrypoint, romInit(), is the first code executed on power-up.  It performsthe minimal setup needed to call the generic C routine romStart() withparameter BOOT_COLD.romInit() masks interrupts in the processor and the interruptcontroller and sets the initial stack pointer (to STACK_ADRS which isdefined in configAll.h).  Other hardware and device initialisation isperformed later in the sysHwInit routine in sysLib.c.The routine sysToMonitor() jumps to a location after the beginning ofromInit, (defined by ROM_WARM_ADRS) to perform a "warm boot".  Thisentry point allows a parameter to be passed to romStart().The routines in this module don't use the "C" frame pointer %r11@ ! orestablish a stack frame.SEE ALSO:.I "ARM Architecture Reference Manual,".I "Samsung KS32C50100 Microcontroller User's Manual,".I "Samsung KS32C5000(A)/50100 Microcontroller Application Notes."*/#define    _ASMLANGUAGE#include "vxWorks.h"#include "sysLib.h"#include "arch/arm/arm.h"#include "arch/arm/mmuArmLib.h"#include "config.h"#include "regs.h"        .data    .globl   FUNC(copyright_wind_river)    .long    FUNC(copyright_wind_river)/* internals */    .globl    FUNC(romInit)    /* start of system code */    .globl    FUNC(sdata)      /* start of data */    .globl    _sdata/* externals */    .globl    FUNC(romStart)    /* system initialization routine */_sdata:FUNC_LABEL(sdata)    .asciz    "start of data"    .balign    4    .text    .balign 4/********************************************************************************* romInit - entry point for VxWorks in ROM** romInit*     (*     int startType    /@ only used by 2nd entry point @/*     )* INTERNAL* sysToMonitor examines the ROM for the first instruction and the string* "Copy" in the third word so if this changes, sysToMonitor must be updated.*/_ARM_FUNCTION(romInit)_romInit:cold:    MOV    r0, #BOOT_COLD    /* fall through to warm boot entry */warm:    B    start    /* copyright notice appears at beginning of ROM (in TEXT segment) */    .ascii   "Copyright 1984-2001 Wind River Systems, Inc."    .balign 4start:    /* disable interrupts in CPU and switch to SVC32 mode */    MRS    r1, cpsr    BIC    r1, r1, #MASK_MODE    ORR    r1, r1, #MODE_SVC32 | I_BIT | F_BIT    MSR    cpsr, r1    MOV    r13, r0    /* Save starttype in r13 so that r0 can be used for other purposes */    /*     * CPU INTERRUPTS DISABLED     *     * disable individual interrupts in the interrupt controller     */    LDR    r2, L$_SBCARM7Intmsk        /* R2->interrupt controller */    MVN    r1, #0                /* &FFFFFFFF */    STR    r1, [r2]            /* disable all interrupt sources */    /*     * If not BOOT_COLD, bypass memory configuration, memory region     * switching etc.     */    CMP    r0, #BOOT_COLD    BNE    HiPosn    /*     * We are now executing in the normal (higher, still in ROM)     * position in the memory map.  Remap memory to post-reset state,     * so that the ROM is not now dual-mapped to zero upwards, but     * RAM is mapped from zero, instead.     */    MOV    r0, #DRAM_TYPE  /* R0-> DRAM type */    CMP    r0, #0x01       /* SDRAM = 0x01, EDO DRAM = 0x00 */    BNE    EDO_RAMSYNC_DRAM:    LDR    r0, L$_SBCARM7Syscfg    LDR    r1, L$_SysCfgSdram    STR    r1, [r0]             /* Cache,WB disable *//* ROM and RAM Configuration(Multiple Load and Store).  Multiple load * LDMIA instruction cannot be used as there is no way to load the * address L$_SystemInitDataSDRAM into a register (LDR Rn,=sym is broken) */    LDR    r1, L$_SystemInitDataSDRAM     LDR    r2, L$_SystemInitDataSDRAM + 0x04    LDR    r3, L$_SystemInitDataSDRAM + 0x08    LDR    r4, L$_SystemInitDataSDRAM + 0x0c    LDR    r5, L$_SystemInitDataSDRAM + 0x10    LDR    r6, L$_SystemInitDataSDRAM + 0x14    LDR    r7, L$_SystemInitDataSDRAM + 0x18    LDR    r8, L$_SystemInitDataSDRAM + 0x1c    LDR    r9, L$_SystemInitDataSDRAM + 0x20    LDR    r10,L$_SystemInitDataSDRAM + 0x24    LDR    r11,L$_SystemInitDataSDRAM + 0x28    LDR    r12,L$_SystemInitDataSDRAM + 0x2c    LDR    r0, L$_SBCARM7Extdbwth         /* Extdbwth Offset : 0x3010 */    STMIA  r0, {r1-r12}    LDR    r1, L$_ClkCon    LDR    r0, L$_SBCARM7ClkCon         /* CLKCON Offset : 0x3000 */    STR    r1, [r0]    LDR    r1, L$_ExtACon    LDR    r2, L$_ExtACon + 0x04    LDR    r0, L$_SBCARM7ExtACon         /* EXTACON Offset : 0x3008 */    STMIA  r0, {r1-r2}/*============================================================= * Copy to DRAM the section of ROM in which we are currently executing. * Soon, we will set the base pointer of DRAM to where the base pointer of * ROM used to be.  At that point the PC will suddenly be set in RAM and * must have legitimate code to execute. *============================================================= */    MOV    r0, #RESET_ROM_START         /* Get pointer to ROM data */    LDR    r1, L$_RomCopySize           /* number of ROM bytes to copy into RAM */    MOV    r2, #RESET_DRAM_START        /* Copy DRAM area base */ROM2SDRAM_COPY_LOOP:    LDR    r3, [r0], #4    STR    r3, [r2], #4    SUBS   r1, r1, #4         /* Down Count */    BNE    ROM2SDRAM_COPY_LOOP/*==================================== * Change Base address of ROM and DRAM *==================================== *//* Multiple load LDMIA instruction cannot be used as there is  * no way to load the address L$_SystemInitDataSDRAM_S into a  * register (LDR Rn,=sym is broken) */    LDR    r1, L$_SystemInitDataSDRAM_S    LDR    r2, L$_SystemInitDataSDRAM_S + 0x04    LDR    r3, L$_SystemInitDataSDRAM_S + 0x08    LDR    r4, L$_SystemInitDataSDRAM_S + 0x0c    LDR    r5, L$_SystemInitDataSDRAM_S + 0x10    LDR    r6, L$_SystemInitDataSDRAM_S + 0x14    LDR    r7, L$_SystemInitDataSDRAM_S + 0x18    LDR    r8, L$_SystemInitDataSDRAM_S + 0x1c    LDR    r9, L$_SystemInitDataSDRAM_S + 0x20    LDR    r10,L$_SystemInitDataSDRAM_S + 0x24    LDR    r11,L$_SystemInitDataSDRAM_S + 0x28    LDR    r12,L$_SystemInitDataSDRAM_S + 0x2c    LDR    r0, L$_SBCARM7Extdbwth     /* ROMCntr Offset : 0x3010 */    STMIA  r0, {r1-r12}    LDR    PC, L$_HiPosn    EDO_RAM:    LDR    r0, L$_SBCARM7Syscfg    LDR    r1, L$_SysCfg    STR    r1, [r0]/* ROM and RAM Configuration(Multiple Load and Store) * Multiple load LDMIA instruction cannot be used as there is  * no way to load the address L$_SystemInitData into a  * register (LDR Rn,=sym is broken) */    LDR    r1, L$_SystemInitData     LDR    r2, L$_SystemInitData + 0x04    LDR    r3, L$_SystemInitData + 0x08    LDR    r4, L$_SystemInitData + 0x0c    LDR    r5, L$_SystemInitData + 0x10    LDR    r6, L$_SystemInitData + 0x14    LDR    r7, L$_SystemInitData + 0x18    LDR    r8, L$_SystemInitData + 0x1c    LDR    r9, L$_SystemInitData + 0x20    LDR    r10,L$_SystemInitData + 0x24    LDR    r11,L$_SystemInitData + 0x28    LDR    r12,L$_SystemInitData + 0x2c    LDR    r0, L$_SBCARM7Extdbwth    /* ROMCntr Offset : 0x3010 */    STMIA  r0, {r1-r12}/*============================================================= * Copy to DRAM the section of ROM in which we are currently executing. * Soon, we will set the base pointer of DRAM to where the base pointer of * ROM used to be.  At that point the PC will suddenly be set in RAM and * must have legitimate code to execute. *============================================================= */    MOV    r0, #RESET_ROM_START         /* Get pointer to ROM data */    LDR    r1, L$_RomCopySize           /* number of ROM bytes to copy into RAM */    MOV    r2, #RESET_DRAM_START        /* Copy DRAM area base */ROM2DRAM_COPY_LOOP:    LDR    r3, [r0], #4    STR    r3, [r2], #4    SUBS   r1, r1, #4            /* Down Count */    BNE    ROM2DRAM_COPY_LOOP/*==================================== * Change Base address of ROM and DRAM *==================================== *//* Multiple load LDMIA instruction cannot be used as there is  * no way to load the address L$_SystemInitData_S into a  * register (LDR Rn,=sym is broken) */    LDR    r1, L$_SystemInitData_S     LDR    r2, L$_SystemInitData_S + 0x04    LDR    r3, L$_SystemInitData_S + 0x08    LDR    r4, L$_SystemInitData_S + 0x0c    LDR    r5, L$_SystemInitData_S + 0x10    LDR    r6, L$_SystemInitData_S + 0x14    LDR    r7, L$_SystemInitData_S + 0x18    LDR    r8, L$_SystemInitData_S + 0x1c    LDR    r9, L$_SystemInitData_S + 0x20    LDR    r10,L$_SystemInitData_S + 0x24    LDR    r11,L$_SystemInitData_S + 0x28    LDR    r12,L$_SystemInitData_S + 0x2c        LDR    r0, L$_SBCARM7Extdbwth    STMIA  r0, {r1-r12}    LDR    PC, L$_HiPosnHiPosn:    /*     * Initialize the stack pointer to just before where the     * uncompress code, copied from ROM to RAM, will run.     */    MOV    r0, r13        /* restore starttype to r0 from r13 */    LDR    sp, L$_STACK_ADDR    MOV    fp, #0            /* zero frame pointer */    /* jump to C entry point in ROM: routine - entry point + ROM base */#if    (CPU == ARMARCH4_T)    LDR    r12, L$_rStrtInRom    ORR    r12, r12, #1        /* force Thumb state */    BX     r12#else    LDR    pc, L$_rStrtInRom#endif    /* (CPU == ARMARCH4_T) *//******************************************************************************//* * PC-relative-addressable pointers - LDR Rn,=sym is broken * note "_" after "$" to stop preprocessor preforming substitution */    .balign    4L$_HiPosn:    .long    ROM_TEXT_ADRS + HiPosn - FUNC(romInit)L$_rStrtInRom:    .long    ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)L$_STACK_ADDR:    .long    STACK_ADRSL$_SBCARM7Intmsk:    .long    SNGKS32C_INTMASKL$_IopModReg:    .long    SNGKS32C_IOPMODL$_IopConReg:    .long    SNGKS32C_IOPCONL$_IopDat:    .long    SNGKS32C_IOPDATAL$_SBCARM7Romcon0:    .long    SNGKS32C_ROMCON0L$_SBCARM7Extdbwth:    .long    SNGKS32C_EXTDBWTHL$_SBCARM7Syscfg:    .long    SNGKS32C_SYSCFGL$_SysCfg:    .long    SYSCONFIG_VALL$_SysCfgSdram:    .long    SYSCONFIG_VAL_SDRAML$_SBCARM7ClkCon:    .long    SNGKS32C_CLKCONL$_ClkCon:    .long    rCLKCONL$_SBCARM7ExtACon:    .long    SNGKS32C_EXTACON0    .long    SNGKS32C_EXTACON1L$_ExtACon:    .long    rEXTACON0    .long    rEXTACON1L$_SystemInitData:    .long    rEXTDBWTH    /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */    .long    rROMCON0     /* 0x0000000 ~ 0x40000, ROM0,256K,2cycle */    .long    rROMCON1     .long    rROMCON2    .long    rROMCON3    .long    rROMCON4    .long    rROMCON5    .long    rDRAMCON0    /* 0x1000000 ~ 0x13FFFFF, DRAM0 4M, */    .long    rDRAMCON1    .long    rDRAMCON2    .long    rDRAMCON3    .long    rREFEXTCON    /* External I/O, Refresh */L$_SystemInitData_S:    .long    rEXTDBWTH    /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */    .long    rROMCON0_S    /* 0x1000000 ~ 0x1040000, ROM0,256K,2cycle */    .long    rROMCON1    .long    rROMCON2    .long    rROMCON3    .long    rROMCON4    .long    rROMCON5    .long    rDRAMCON0_S     /* 0x0000000 ~ 0x03FFFFF, DRAM0 */    .long    rDRAMCON1    .long    rDRAMCON2    .long    rDRAMCON3    .long    rREFEXTCON    /* External I/O, Refresh *//*====================================================== * SDRAM System Initialize Data (KS32C50100 only) *====================================================== */L$_SystemInitDataSDRAM:    .long    rEXTDBWTH    /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */    .long    rROMCON0    /* 0x0000000 ~ 0x40000, ROM0,256K,2cycle */    .long    rROMCON1    .long    rROMCON2    .long    rROMCON3    .long    rROMCON4    .long    rROMCON5    .long    rSDRAMCON0    /* 0x1000000 ~ 0x13FFFFF, DRAM0 4M, */    .long    rSDRAMCON1    .long    rSDRAMCON2    .long    rSDRAMCON3    .long    rSREFEXTCON    /* External I/O, Refresh */L$_SystemInitDataSDRAM_S:    .long    rEXTDBWTH    /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */    .long    rROMCON0_S    /* 0x1000000 ~ 0x1040000, ROM0,256K,2cycle */    .long    rROMCON1    .long    rROMCON2    .long    rROMCON3    .long    rROMCON4    .long    rROMCON5    .long    rSDRAMCON0_S    /* 0x0000000 ~ 0x03FFFFF, DRAM0 4M, */    .long    rSDRAMCON1    .long    rSDRAMCON2    .long    rSDRAMCON3    .long    rSREFEXTCON    /* External I/O, Refresh */L$_pSystemInitData:    .long    L$_SystemInitDataL$_pSystemInitData_S:    .long    L$_SystemInitData_SL$_pSystemInitDataSDRAM:    .long    L$_SystemInitDataSDRAML$_pSystemInitDataSDRAM_S:    .long    L$_SystemInitDataSDRAM_SL$_RomCopySize:    .long    L$_RomCopySize - FUNC(romInit)